公开(公告)号：US4958206A

公开(公告)日：1990-09-18

申请号：US212452

申请日：1988-06-28

申请人： Clarence W. Teng ,  Robert R. Doering ,  Dirk Anderson

发明人： Clarence W. Teng ,  Robert R. Doering ,  Dirk Anderson

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： A trench (28) of a DRAM cell is formed in a (p-) epitaxial layer (10) and a silicon substrate (12), and a storage oxide (32) is grown on the sidewalls (30) of the trench (28). A highly doped polysilicon capacitor electrode (34) is formed in the trench (28). A portion (52) of the storage oxide (32) is removed from a selected side of the sidewalls (30), and a plug (68) is deposited therein and etched back so that the electrode (34) is connected to the epitaxial layer (10). A thermal cycle is used to diffuse dopant from the capacitor electrode (34) into and through the plug (68) and into the adjacent semiconductor layer (10) to make the plug (68) conductive and to form a source region (66) of a pass gate transistor of the cell.

摘要翻译： 在（p-）外延层（10）和硅衬底（12）中形成DRAM单元的沟槽（28），并且在沟槽（28）的侧壁（30）上生长存储氧化物（32） ）。 在沟槽（28）中形成高掺杂多晶硅电容器电极（34）。 存储氧化物（32）的一部分（52）从侧壁（30）的选定侧被去除，并且在其中沉积插塞（68）并被回蚀，使得电极（34）连接到外延层 （10）。 热循环用于将掺杂剂从电容器电极（34）扩散入并穿过插塞（68）并进入相邻的半导体层（10）以使插头（68）导电并形成源极区域（66） 电池的通栅晶体管。

公开(公告)号：US4958212A

公开(公告)日：1990-09-18

申请号：US292285

申请日：1988-12-30

申请人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

发明人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

IPC分类号： H01L27/108

CPC分类号： H01L27/10841

摘要： An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).

摘要翻译： 形成改进的存储单元布局（54），包括形成在半导体衬底（58）中的沟槽单元（60）。 存储单元布局（54）包括用于存储和访问电荷的位线（56）和字线（62）。 电荷存储在由导体（68），绝缘区（70）和半导体衬底（58）形成的电容器上。 位线（56）主要与沟槽单元（60）相切，或者可以围绕其周边。 字线（62）覆盖在沟槽单元（60）上并在其中延伸，并且还可以由窄于沟槽单元（60）的宽度形成。

公开(公告)号：US5156992A

公开(公告)日：1992-10-20

申请号：US720542

申请日：1991-06-25

申请人： Clarence W. Teng ,  Robert R. Doering

发明人： Clarence W. Teng ,  Robert R. Doering

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10841

摘要： A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.

摘要翻译： 存储单元包括在柱的侧壁上的半导体柱和绝缘体。 存储单元的导电电容器包括邻近绝缘体的第一电极。 存储单元的晶体管形成在柱中，并且包括耦合到第一电极的第一源极/漏极区域，栅极和第二源极/漏极区域。

公开(公告)号：US4916524A

公开(公告)日：1990-04-10

申请号：US300467

申请日：1989-01-23

申请人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

发明人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

IPC分类号： H01L21/225 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L21/2254 ,  H01L27/10841

摘要： The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.

摘要翻译： 本发明的所描述的实施例提供了包括形成在单个沟槽内的存储单元的结构和制造这些结构的方法。 在半导体衬底的表面形成沟槽。 沟槽的底部填充有多晶硅以形成存储电容器的一个板。 该基板用作电容器的另一个板。 然后用绝缘材料如二氧化硅填充沟槽的剩余部分。 然后当将侧壁的一部分和沟槽的顶部部分向下切割到多晶电容器板时，将图案蚀刻到二氧化硅中。 然后在多晶电容器板和衬底之间形成接触。 掺杂原子通过接触扩散以在沟槽的侧壁上形成源区。 通过氧化形成栅极绝缘体，并且在与沟槽的口相邻的沟槽的表面处形成漏极。 然后，在沟槽上部的开口部分形成导电材料，从而形成将存储电容器的上板连接到半导体衬底的表面上的漏极区域的晶体管。

公开(公告)号：US4580330A

公开(公告)日：1986-04-08

申请号：US621019

申请日：1984-06-15

申请人： Gordon P. Pollack ,  Clarence W. Teng ,  William R. Hunter ,  Christopher Slawinski ,  Robert R. Doering

发明人： Gordon P. Pollack ,  Clarence W. Teng ,  William R. Hunter ,  Christopher Slawinski ,  Robert R. Doering

IPC分类号： H01L29/78 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L29/0638 ,  H01L21/32 ,  H01L21/76232 ,  Y10S148/05

摘要： An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.

摘要翻译： 一种集成电路隔离技术，其中通过在将第二氮化物（防止侵入的侧壁氮化物）添加到第一氮化物（覆盖护城河区域）之前执行底切和回填来改进现有技术的氮化物 - 侧壁方法。 因此，使两个氮化物之间的对接更牢固，并且不会发生在护环氮化物和侧壁氮化物之间的对接接合处的局部鸟鸣。

公开(公告)号：US4830978A

公开(公告)日：1989-05-16

申请号：US26356

申请日：1987-03-16

申请人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

发明人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

IPC分类号： H01L27/10 ,  H01L21/225 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L21/2254 ,  H01L27/10841

摘要： The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.

公开(公告)号：US4561172A

公开(公告)日：1985-12-31

申请号：US621023

申请日：1984-06-15

申请人： Christopher Slawinski ,  Robert R. Doering ,  Clarence W. Teng

发明人： Christopher Slawinski ,  Robert R. Doering ,  Clarence W. Teng

IPC分类号： H01L29/78 ,  H01L21/308 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76232 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/76237 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/117

摘要： A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.

摘要翻译： 侧壁氮化物隔离技术通过在氮化物蚀刻步骤期间防止氮化物护层护层的任何变薄来净化横向氧化物侵蚀的过程控制，其从硅中的蚀刻凹槽的底部清除侧壁氮化物层。 这通过首先在氧化物/氮化物/氧化物堆叠中而不是现有技术的氮化物/氧化物堆叠图案化沟槽区域来完成。

公开(公告)号：US5364812A

公开(公告)日：1994-11-15

申请号：US86524

申请日：1993-07-01

申请人： Masaaki Yashiro ,  Shigeki Morinaga ,  Clarence W. Teng

发明人： Masaaki Yashiro ,  Shigeki Morinaga ,  Clarence W. Teng

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10829 ,  Y10S257/90

摘要： The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.

摘要翻译： 本发明的所描述的实施例提供了一种用于制造包括该单元的存储单元和存储器阵列的存储单元和方法。 存储单元是具有形成在基板（16）的主面的表面上的晶体管（1-1-2）的沟槽电容器型，并且在周围形成有基板的电容器（2-1-2） 的沟渠 电容器和晶体管通过与衬底具有相反导电类型的掩埋的重掺杂区域（26）连接。 具有与掩埋掺杂区相同的掺杂类型的掺杂存储区（24）围绕沟槽。 通过电介质层（32），在与沟槽区分开的沟槽中形成场板（30）。 场板延伸到存储单元之间的隔离区域，从而使用最小的表面积来提供电池之间的隔离。 自对准工艺用于形成栅极晶体管的源极（14）和漏极（12），晶体管的源极和掩埋掺杂层之间的自动连接由掩埋的N +层制成。 形成侧壁氮化硅钝化丝（38）以保护第一（30）和第二（3-3,3-4）多晶硅层之间的层间绝缘体区域的侧壁。

公开(公告)号：US5671175A

公开(公告)日：1997-09-23

申请号：US670079

申请日：1996-06-26

申请人： Jiann Liu ,  Clarence W. Teng

发明人： Jiann Liu ,  Clarence W. Teng

IPC分类号： H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10808 ,  Y10S257/908

摘要： A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (112). A second polysilicon plug (110) connects the storage capacitor (150) to the other source/drain region (120a&c) of the pass transistor. Both polysilicon plugs (110, 112) extend through an interlevel dielectric layer (116) to one of the source/drain region (120a-c) of the pass transistor, but neither extends over the isolation structure (108). If desired, either the storage capacitor (150) or the bitline (140) may be offset from the source/drain regions (120a-c).

摘要翻译： 具有降低的位线电容的DRAM阵列（100）。 DRAM单元包括传输晶体管和存储电容器（150）。 隔离结构（108）围绕DRAM单元。 位线（140）使用第一多晶硅插头（112）连接到传输晶体管的源极/漏极区域（120b）。 第二多晶硅插头（110）将存储电容器（150）连接到传输晶体管的另一个源极/漏极区域（120a和c）。 两个多晶硅插头（110,112）延伸穿过层间电介质层（116）到通过晶体管的源极/漏极区域（120a-c）之一，但是两者都不延伸到隔离结构（108）上。 如果需要，存储电容器（150）或位线（140）可能偏离源极/漏极区域（120a-c）。

公开(公告)号：US5595925A

公开(公告)日：1997-01-21

申请号：US236745

申请日：1994-04-29

申请人： Ih-Chin Chen ,  Hisashi Shichijo ,  Clarence W. Teng

发明人： Ih-Chin Chen ,  Hisashi Shichijo ,  Clarence W. Teng

IPC分类号： H01L21/8238 ,  H01L21/8226 ,  H01L21/8242 ,  H01L27/082 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

摘要翻译： 动态随机存取存储器件（10）包括三个单独的部分 - 输入/输出部分（12），外围晶体管部分（14）和存储器阵列部分（16），全部形成在p型衬底层 18）。 动态随机存取存储器件（10）可以为每个部分采用单独的衬底偏置电压。 输入/输出部分（12）具有通过n型阱区域（20）与p-型衬底层（18）隔离的p-型区域（22）。 外围晶体管部分（14）具有p型区域（36），其可以通过可选的n型阱区域（40）与p型衬底层（18）隔离，用于那些需要不同衬底偏置的器件 外围晶体管部分（14）和存储器阵列部分（16）之间的电压。