公开(公告)号：US4958206A

公开(公告)日：1990-09-18

申请号：US212452

申请日：1988-06-28

申请人： Clarence W. Teng ,  Robert R. Doering ,  Dirk Anderson

发明人： Clarence W. Teng ,  Robert R. Doering ,  Dirk Anderson

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： A trench (28) of a DRAM cell is formed in a (p-) epitaxial layer (10) and a silicon substrate (12), and a storage oxide (32) is grown on the sidewalls (30) of the trench (28). A highly doped polysilicon capacitor electrode (34) is formed in the trench (28). A portion (52) of the storage oxide (32) is removed from a selected side of the sidewalls (30), and a plug (68) is deposited therein and etched back so that the electrode (34) is connected to the epitaxial layer (10). A thermal cycle is used to diffuse dopant from the capacitor electrode (34) into and through the plug (68) and into the adjacent semiconductor layer (10) to make the plug (68) conductive and to form a source region (66) of a pass gate transistor of the cell.

摘要翻译： 在（p-）外延层（10）和硅衬底（12）中形成DRAM单元的沟槽（28），并且在沟槽（28）的侧壁（30）上生长存储氧化物（32） ）。 在沟槽（28）中形成高掺杂多晶硅电容器电极（34）。 存储氧化物（32）的一部分（52）从侧壁（30）的选定侧被去除，并且在其中沉积插塞（68）并被回蚀，使得电极（34）连接到外延层 （10）。 热循环用于将掺杂剂从电容器电极（34）扩散入并穿过插塞（68）并进入相邻的半导体层（10）以使插头（68）导电并形成源极区域（66） 电池的通栅晶体管。

公开(公告)号：US5156992A

公开(公告)日：1992-10-20

申请号：US720542

申请日：1991-06-25

申请人： Clarence W. Teng ,  Robert R. Doering

发明人： Clarence W. Teng ,  Robert R. Doering

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10841

摘要： A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.

摘要翻译： 存储单元包括在柱的侧壁上的半导体柱和绝缘体。 存储单元的导电电容器包括邻近绝缘体的第一电极。 存储单元的晶体管形成在柱中，并且包括耦合到第一电极的第一源极/漏极区域，栅极和第二源极/漏极区域。

公开(公告)号：US4958212A

公开(公告)日：1990-09-18

申请号：US292285

申请日：1988-12-30

申请人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

发明人： Clarence W. Teng ,  William F. Richardson ,  Robert R. Doering ,  Ashwin H. Shah ,  Bing W. Shen ,  Mark Bordelon

IPC分类号： H01L27/108

CPC分类号： H01L27/10841

摘要： An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).

摘要翻译： 形成改进的存储单元布局（54），包括形成在半导体衬底（58）中的沟槽单元（60）。 存储单元布局（54）包括用于存储和访问电荷的位线（56）和字线（62）。 电荷存储在由导体（68），绝缘区（70）和半导体衬底（58）形成的电容器上。 位线（56）主要与沟槽单元（60）相切，或者可以围绕其周边。 字线（62）覆盖在沟槽单元（60）上并在其中延伸，并且还可以由窄于沟槽单元（60）的宽度形成。

公开(公告)号：US4830978A

公开(公告)日：1989-05-16

申请号：US26356

申请日：1987-03-16

申请人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

发明人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

IPC分类号： H01L27/10 ,  H01L21/225 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L21/2254 ,  H01L27/10841

摘要： The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.

公开(公告)号：US4561172A

公开(公告)日：1985-12-31

申请号：US621023

申请日：1984-06-15

申请人： Christopher Slawinski ,  Robert R. Doering ,  Clarence W. Teng

发明人： Christopher Slawinski ,  Robert R. Doering ,  Clarence W. Teng

IPC分类号： H01L29/78 ,  H01L21/308 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/76232 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/76237 ,  Y10S148/085 ,  Y10S148/086 ,  Y10S148/117

摘要： A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.

摘要翻译： 侧壁氮化物隔离技术通过在氮化物蚀刻步骤期间防止氮化物护层护层的任何变薄来净化横向氧化物侵蚀的过程控制，其从硅中的蚀刻凹槽的底部清除侧壁氮化物层。 这通过首先在氧化物/氮化物/氧化物堆叠中而不是现有技术的氮化物/氧化物堆叠图案化沟槽区域来完成。

公开(公告)号：US4916524A

公开(公告)日：1990-04-10

申请号：US300467

申请日：1989-01-23

申请人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

发明人： Clarence W. Teng ,  Robert R. Doering ,  Ashwin H. Shah

IPC分类号： H01L21/225 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L21/2254 ,  H01L27/10841

摘要： The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.

摘要翻译： 本发明的所描述的实施例提供了包括形成在单个沟槽内的存储单元的结构和制造这些结构的方法。 在半导体衬底的表面形成沟槽。 沟槽的底部填充有多晶硅以形成存储电容器的一个板。 该基板用作电容器的另一个板。 然后用绝缘材料如二氧化硅填充沟槽的剩余部分。 然后当将侧壁的一部分和沟槽的顶部部分向下切割到多晶电容器板时，将图案蚀刻到二氧化硅中。 然后在多晶电容器板和衬底之间形成接触。 掺杂原子通过接触扩散以在沟槽的侧壁上形成源区。 通过氧化形成栅极绝缘体，并且在与沟槽的口相邻的沟槽的表面处形成漏极。 然后，在沟槽上部的开口部分形成导电材料，从而形成将存储电容器的上板连接到半导体衬底的表面上的漏极区域的晶体管。

公开(公告)号：US4580330A

公开(公告)日：1986-04-08

申请号：US621019

申请日：1984-06-15

申请人： Gordon P. Pollack ,  Clarence W. Teng ,  William R. Hunter ,  Christopher Slawinski ,  Robert R. Doering

发明人： Gordon P. Pollack ,  Clarence W. Teng ,  William R. Hunter ,  Christopher Slawinski ,  Robert R. Doering

IPC分类号： H01L29/78 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L29/0638 ,  H01L21/32 ,  H01L21/76232 ,  Y10S148/05

摘要： An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.

摘要翻译： 一种集成电路隔离技术，其中通过在将第二氮化物（防止侵入的侧壁氮化物）添加到第一氮化物（覆盖护城河区域）之前执行底切和回填来改进现有技术的氮化物 - 侧壁方法。 因此，使两个氮化物之间的对接更牢固，并且不会发生在护环氮化物和侧壁氮化物之间的对接接合处的局部鸟鸣。

公开(公告)号：US5374580A

公开(公告)日：1994-12-20

申请号：US129011

申请日：1993-09-30

申请人： David A. Baglee ,  Robert R. Doering ,  Gregory J. Armstrong

发明人： David A. Baglee ,  Robert R. Doering ,  Gregory J. Armstrong

IPC分类号： H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10829 ,  Y10S438/981

摘要： A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

摘要翻译： 动态单晶体管读/写存储单元采用沟槽电容器来增加存储电荷的大小。 在与N +位线结构相似的扩散的N +电容器区域，将沟槽蚀刻到硅表面中，然后在位线上和电容器区域上而不是在沟槽中生长厚的氧化物。 电容器的上板是延伸到沟槽中的多晶硅层，并且还在硅棒的表面上形成场板隔离。 难熔金属字线在多晶硅场板的一个孔处形成存取晶体管的栅极。

公开(公告)号：US5170234A

公开(公告)日：1992-12-08

申请号：US758318

申请日：1991-08-27

申请人： David A. Baglee ,  Robert R. Doering ,  Gregory J. Armstrong

发明人： David A. Baglee ,  Robert R. Doering ,  Gregory J. Armstrong

IPC分类号： H01L27/108

CPC分类号： H01L27/10829 ,  Y10S438/981

摘要： A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A word line forms the gate of the access transistor at a hole in the polysilicon field plate.

摘要翻译： 动态单晶体管读/写存储单元采用沟槽电容器来增加存储电荷的大小。 在与N +位线结构相似的扩散的N +电容器区域，将沟槽蚀刻到硅表面中，然后在位线上和电容器区域上而不是在沟槽中生长厚的氧化物。 电容器的上板是延伸到沟槽中的多晶硅层，并且还在硅棒的表面上形成场板隔离。 字线在多晶硅场板的孔处形成存取晶体管的栅极。

公开(公告)号：US06990035B2

公开(公告)日：2006-01-24

申请号：US10727888

申请日：2003-12-03

申请人： Donald J. Redwine ,  Robert R. Doering

发明人： Donald J. Redwine ,  Robert R. Doering

IPC分类号： G11C7/00

CPC分类号： G11C11/417

摘要： A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal (224) of a memory cell having a first (612) and a second (614) data terminal. A data bit is stored in a memory cell (600,602,604,606). A second voltage (VDA) different from the first voltage is applied to the power terminal. A third voltage (Ground) is applied to the first and second data terminals. The first voltage is applied to the power terminal.

摘要翻译： 公开了一种操作存储电路以减少待机电流的方法。 该方法包括将第一电压（Vdd）应用于具有第一（612）和第二（614）数据端的存储单元的电源端子（224）。 数据位存储在存储单元（600,602,604,606）中。 与第一电压不同的第二电压（VDA）被施加到电源端子。 第三电压（Ground）被施加到第一和第二数据端子。 第一个电压被施加到电源端子。