Methods of forming phase-changeable memory devices using growth-enhancing and growth-inhibiting layers for phase-changeable materials
    4.
    发明授权
    Methods of forming phase-changeable memory devices using growth-enhancing and growth-inhibiting layers for phase-changeable materials 失效
    使用用于相变材料的生长增强和生长抑制层形成相变存储器件的方法

    公开(公告)号:US07772067B2

    公开(公告)日:2010-08-10

    申请号:US12039370

    申请日:2008-02-28

    IPC分类号: H01L21/336

    摘要: Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.

    摘要翻译: 形成相变存储器件的方法包括抑制相变材料中的空隙形成的技术,以增加器件的可靠性。 抑制空隙形成的这些技术使用电绝缘的生长抑制层来引导存储单元(例如,PRAM单元)内的相变材料区域的形成。 特别地,形成集成电路存储器件的方法包括在衬底上形成其中具有开口的层间绝缘层,然后用支撑生长的种子层(即生长增强层)来衬套开口的侧壁 相变材料。 然后在围绕开口的层间绝缘层的一部分上选择性地形成电绝缘的生长抑制层。 生长抑制层的形成之后是选择性地生长开口中的相变材料区域,而不是在生长抑制层上生长的步骤。

    METHODS OF FORMING PHASE-CHANGEABLE MEMORY DEVICES USING GROWTH-ENHANCING AND GROWTH-INHIBITING LAYERS FOR PHASE-CHANGEABLE MATERIALS
    5.
    发明申请
    METHODS OF FORMING PHASE-CHANGEABLE MEMORY DEVICES USING GROWTH-ENHANCING AND GROWTH-INHIBITING LAYERS FOR PHASE-CHANGEABLE MATERIALS 失效
    使用生长增强和生长抑制层形成可更换材料的相变可变存储器件的方法

    公开(公告)号:US20090130797A1

    公开(公告)日:2009-05-21

    申请号:US12039370

    申请日:2008-02-28

    IPC分类号: H01L45/00

    摘要: Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer to guide the formation of a phase-changeable material region within a memory cell (e.g., PRAM cell). In particular, methods of forming an integrated circuit memory device include forming an interlayer insulating layer having an opening therein, on a substrate, and then lining sidewalls of the opening with a seed layer (i.e., growth-enhancing layer) that supports growth of a phase-changeable material thereon. An electrically insulating growth-inhibiting layer is then selectively formed on a portion of the interlayer insulating layer surrounding the opening. The formation of the growth-inhibiting layer is followed by a step to selectively grow a phase-changeable material region in the opening, but not on the growth-inhibiting layer.

    摘要翻译: 形成相变存储器件的方法包括抑制相变材料中的空隙形成的技术,以增加器件的可靠性。 抑制空隙形成的这些技术使用电绝缘的生长抑制层来引导存储单元(例如,PRAM单元)内的相变材料区域的形成。 特别地,形成集成电路存储器件的方法包括在衬底上形成其中具有开口的层间绝缘层,然后用支撑生长的种子层(即生长增强层)来衬套开口的侧壁 相变材料。 然后在围绕开口的层间绝缘层的一部分上选择性地形成电绝缘的生长抑制层。 生长抑制层的形成之后是选择性地生长开口中的相变材料区域,而不是在生长抑制层上生长的步骤。

    VARIABLE RESISTANCE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME
    7.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开
    可变电阻存储器件,其制造方法和包括其的存储器系统

    公开(公告)号:US20100124800A1

    公开(公告)日:2010-05-20

    申请号:US12617754

    申请日:2009-11-13

    IPC分类号: H01L21/06

    摘要: A method of fabricating a variable resistance memory device includes a plasma etching process to remove contaminants from variable resistance material that forms variable resistance elements of the device. Bottom electrodes are formed on a semiconductor substrate. Next, an interlayer dielectric layer having trenches that expose the bottom electrodes is formed on the substrate. Then a layer of variable resistance material is formed. The variable resistance material covers the interlayer dielectric layer and fills the trenches. The variable resistance material is then planarized down to at least the top surface of the interlayer dielectric layer, thereby leaving elements of the variable resistance material in the trenches. The variable resistance material in the trenches is etched to remove contaminants, produced as a result of the planarizing process, from atop the variable resistance material in the trenches. A top electrode is then formed on the variable resistance material.

    摘要翻译: 制造可变电阻存储器件的方法包括等离子体蚀刻工艺,以从形成该器件的可变电阻元件的可变电阻材料中除去污染物。 底电极形成在半导体衬底上。 接下来,在基板上形成具有露出底部电极的沟槽的层间电介质层。 然后形成一层可变电阻材料。 可变电阻材料覆盖层间电介质层并填充沟槽。 然后将可变电阻材料平坦化到至少层间电介质层的顶表面,从而将可变电阻材料的元件留在沟槽中。 蚀刻沟槽中的可变电阻材料,以从沟槽中的可变电阻材料的顶部去除作为平坦化处理的结果产生的污染物。 然后在可变电阻材料上形成顶部电极。