公开(公告)号：US07933154B2

公开(公告)日：2011-04-26

申请号：US12213937

申请日：2008-06-26

申请人： Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

发明人： Myoung Gon Kang ,  Ki Tae Park ,  Doo Gon Kim ,  Yeong Taek Lee

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

摘要： A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.

摘要翻译： 非易失性存储器件包括存储单元阵列，经由多个位线从其读取数据，存储单元阵列包括具有分别与多个字线连接的门的多个存储器单元，第一类型全局字线解码器，被配置为选择性地施加n 不同的电压，其中n是大于或等于3的整数，与程序模式中的多个字线的相应字线相对应，并且第二类型全局字线解码器被配置为选择性地将（n-1）个不同的电压应用于相应的 在编程模式下的多个字线的字线，第二类全局字线解码器具有比第一类全局字线解码器少的开关元件。

公开(公告)号：US07848155B2

公开(公告)日：2010-12-07

申请号：US12165861

申请日：2008-07-01

申请人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

发明人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/349 ,  G11C29/82

摘要： Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller.

摘要翻译： 操作非易失性存储器件的方法可以补偿在块擦除操作期间由开销数据编程引起的阈值电压干扰。 这些方法包括擦除非易失性存储器单元的备用阵列和与备用阵列共享字线的非易失性存储单元的相应主阵列。 这种擦除操作之后是将更新的开销数据（例如，擦除计数）写入备用阵列中，然后执行软程序操作。 该软编程操作在主阵列的至少第一部分上执行，从而缩小主阵列的第一部分内的擦除的存储器单元的阈值电压分布。 然后，软程序操作之后是至少验证主阵列的第一部分的擦除状态的操作以及用于通知非易失性存储器单元的主阵列和备用阵列已经被适当地擦除到存储器控制器的操作。

公开(公告)号：US20090010073A1

公开(公告)日：2009-01-08

申请号：US12165861

申请日：2008-07-01

申请人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

发明人： Doo Gon Kim ,  Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C16/06 ,  G11C8/00

CPC分类号： G11C16/3404 ,  G11C16/349 ,  G11C29/82

摘要： Methods of operating non-volatile memory devices can compensate for threshold voltage disturbances caused by overhead data programming during block erase operations. These methods include erasing a spare array of nonvolatile memory cells and a corresponding main array of nonvolatile memory cells that shares word lines with the spare array. This erasing operation is followed by writing updated overhead data (e.g., an erase count) into the spare array and then performing a soft program operation. This soft program operation is performed on at least a first portion of the main array to thereby narrow a threshold voltage distribution of erased memory cells within the first portion of the main array. The soft program operation is then followed by an operation to verify an erased status of at least the first portion of the main array and an operation to communicate that the main and spare arrays of nonvolatile memory cells have been properly erased to a memory controller.

摘要翻译： 操作非易失性存储器件的方法可以补偿在块擦除操作期间由开销数据编程引起的阈值电压干扰。 这些方法包括擦除非易失性存储器单元的备用阵列和与备用阵列共享字线的非易失性存储单元的相应主阵列。 这种擦除操作之后是将更新的开销数据（例如，擦除计数）写入备用阵列中，然后执行软程序操作。 该软编程操作在主阵列的至少第一部分上执行，从而缩小主阵列的第一部分内的擦除的存储器单元的阈值电压分布。 然后，软程序操作之后是至少验证主阵列的第一部分的擦除状态的操作以及用于通知非易失性存储器单元的主阵列和备用阵列已经被适当地擦除到存储器控制器的操作。

公开(公告)号：US20100265769A1

公开(公告)日：2010-10-21

申请号：US12823726

申请日：2010-06-25

申请人： SOON WOOK HWANG ,  Ki Tae Park ,  Yeong Taek Lee

发明人： SOON WOOK HWANG ,  Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C7/227 ,  G11C16/0483

摘要： An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

摘要翻译： 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。

公开(公告)号：US08139406B2

公开(公告)日：2012-03-20

申请号：US12213938

申请日：2008-06-26

申请人： Ki Tae Park ,  Yeong Taek Lee

发明人： Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C11/40

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2216/14

摘要： A programming method for a non-volatile memory system includes storing multi-page program data and buffering the multi-page program data from a page buffer to a memory block and programming the multi-page program data through a predetermined number of program operations. The programming the multi-page program data includes programming memory cells of the memory block using a first threshold voltage lower than a desired threshold voltage based on the multi-page program data sequentially buffered by the page buffer in units of pages and programming the memory cells using the desired threshold voltage by increasing a threshold voltage of the memory cells by a predetermined level at each successive program operation.

摘要翻译： 用于非易失性存储器系统的编程方法包括存储多页程序数据并将多页程序数据从页缓冲器缓冲到存储块，并通过预定数量的程序操作对多页程序数据进行编程。 多页面程序数据的编程包括使用低于所需阈值电压的第一阈值电压来编程存储器块，该第一阈值电压是基于由页缓冲器以页为单位顺序缓冲的多页程序数据，并对存储单元进行编程 通过在每个连续的程序操作中将存储器单元的阈值电压提高预定的电平来使用所需的阈值电压。

公开(公告)号：US20090003067A1

公开(公告)日：2009-01-01

申请号：US12213937

申请日：2008-06-26

申请人： Myoung Gon Kang ,  Ki Tae Park ,  Dao Gon Kim ,  Yeong Taek Lee

发明人： Myoung Gon Kang ,  Ki Tae Park ,  Dao Gon Kim ,  Yeong Taek Lee

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

摘要： A non-volatile memory device includes a memory cell array from which data is read via a plurality of bitlines, which includes a plurality of memory cells having gates respectively connected with a plurality of wordlines, a first type global wordline decoder configured to selectively apply n different voltages, where n is an integer greater than or equal to 3, to a corresponding wordline of the plurality of wordlines in a program mode, and a second type global wordline decoder configured to selectively apply (n−1) different voltages to a corresponding wordline of the plurality of wordlines in the program mode, the second type global wordline decoder having fewer switching elements than the first type global wordline decoder.

摘要翻译： 非易失性存储器件包括存储单元阵列，经由多个位线从其读取数据，存储单元阵列包括具有分别与多个字线连接的门的多个存储器单元，第一类型全局字线解码器，被配置为选择性地施加n 不同的电压，其中n是大于或等于3的整数，与程序模式中的多个字线的相应字线相对应，并且第二类型全局字线解码器被配置为选择性地将（n-1）个不同的电压应用于相应的 在编程模式下的多个字线的字线，第二类全局字线解码器具有比第一类全局字线解码器少的开关元件。

公开(公告)号：US20090003066A1

公开(公告)日：2009-01-01

申请号：US12213938

申请日：2008-06-26

申请人： Ki Tae Park ,  Yeong Taek Lee

发明人： Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2216/14

摘要： A programming method for a non-volatile memory system includes storing multi-page program data and buffering the multi-page program data from a page buffer to a memory block and programming the multi-page program data through a predetermined number of program operations. The programming the multi-page program data includes programming memory cells of the memory block using a first threshold voltage lower than a desired threshold voltage based on the multi-page program data sequentially buffered by the page buffer in units of pages and programming the memory cells using the desired threshold voltage by increasing a threshold voltage of the memory cells by a predetermined level at each successive program operation.

摘要翻译： 用于非易失性存储器系统的编程方法包括存储多页程序数据并将多页程序数据从页缓冲器缓冲到存储块，并通过预定数量的程序操作对多页程序数据进行编程。 多页面程序数据的编程包括使用低于所需阈值电压的第一阈值电压来编程存储器块，该第一阈值电压是基于由页缓冲器以页为单位顺序缓冲的多页程序数据，并对存储单元进行编程 通过在每个连续的程序操作中将存储器单元的阈值电压提高预定的电平来使用所需的阈值电压。

公开(公告)号：US08027199B2

公开(公告)日：2011-09-27

申请号：US12823726

申请日：2010-06-25

申请人： Soon Wook Hwang ,  Ki Tae Park ,  Yeong Taek Lee

发明人： Soon Wook Hwang ,  Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C7/227 ,  G11C16/0483

摘要： An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

摘要翻译： 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。

公开(公告)号：US20080316825A1

公开(公告)日：2008-12-25

申请号：US12142460

申请日：2008-06-19

申请人： Soon Wook HWANG ,  Ki Tae Park ,  Yeong Taek Lee

发明人： Soon Wook HWANG ,  Ki Tae Park ,  Yeong Taek Lee

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C16/08 ,  G11C7/227 ,  G11C16/0483

摘要： An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

摘要翻译： 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。

公开(公告)号：US20070147161A1

公开(公告)日：2007-06-28

申请号：US11594278

申请日：2006-11-08

申请人： Young Ok Cho ,  Yeong Taek Lee

发明人： Young Ok Cho ,  Yeong Taek Lee

IPC分类号： G11C8/00 ,  G11C5/02

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C7/18 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4097

摘要： A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding drivers are arranged in sense amplifier regions. Further, the wiring for signals to be transmitted from decoding drivers to a corresponding sub-word line driver is arranged in adjacent sub-arrays. Accordingly, the area of word line regions can be remarkably reduced. Further, the wiring required to transmit pre-decoding signals that are provided to decoding drivers is also arranged in adjacent sub-arrays. Accordingly, the area of sense amplifier regions can be greatly reduced. Consequently, the semiconductor memory device of the present invention is advantageous in that the layout area thereof is notably reduced.

摘要翻译： 半导体存储器件具有最小化读出放大器和字线驱动器区域所需的面积的布局。 在本发明的半导体存储器件中，解码驱动器被布置在读出放大器区域中。 此外，将从解码驱动器发送到对应的子字线驱动器的信号的布线被布置在相邻的子阵列中。 因此，可以显着地减少字线区域的面积。 此外，发送提供给解码驱动器的预解码信号所需的布线也布置在相邻的子阵列中。 因此，可以大大降低读出放大器区域的面积。 因此，本发明的半导体存储器件的优点在于其布局面积明显减小。