公开(公告)号：US20070190718A1

公开(公告)日：2007-08-16

申请号：US11275604

申请日：2006-01-19

申请人： Douglas Coolbaugh ,  Keith Downes ,  Peter Lindgren ,  Anthony Stamper

发明人： Douglas Coolbaugh ,  Keith Downes ,  Peter Lindgren ,  Anthony Stamper

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L21/4763 ,  H01L21/302

CPC分类号： H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

摘要翻译： 一种方法和半导体器件。 在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。 该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

公开(公告)号：US20070065966A1

公开(公告)日：2007-03-22

申请号：US11162661

申请日：2005-09-19

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper

IPC分类号： H01L21/00 ,  H01L29/84

CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

公开(公告)号：US20070194390A1

公开(公告)日：2007-08-23

申请号：US11276282

申请日：2006-02-22

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  John Florkey ,  Heidi Greer ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/76

CPC分类号： H01L29/8605 ,  H01L27/0802 ,  H01L28/20

摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

摘要翻译： 本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。 根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。 本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

公开(公告)号：US20070057343A1

公开(公告)日：2007-03-15

申请号：US11162471

申请日：2005-09-12

申请人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

发明人： Anil Chinthakindi ,  Douglas Coolbaugh ,  Keith Downes ,  Ebenezer Eshun ,  Zhong-Xiang He ,  Robert Rassel ,  Anthony Stamper ,  Kunal Vaed

IPC分类号： H01L29/00

CPC分类号： H01L28/40

摘要： A Metal Insulator-Metal (MIM) capacitor is formed on a semiconductor substrate with a base comprising a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. An ancillary MIM capacitor plate is selected either a lower electrode formed on the STI region in the semiconductor substrate or a doped well formed in the top surface of the semiconductor substrate. A capacitor HiK dielectric layer is formed on or above the MIM capacitor lower plate. A second MIM capacitor plate is formed on the HiK dielectric layer above the MIM capacitor lower plate.

摘要翻译： 金属绝缘体 - 金属（MIM）电容器形成在半导体衬底上，其基底包括具有顶表面的半导体衬底，并且包括形成在从浅沟槽隔离（STI）区域中形成的区域和具有外表面的掺杂阱 与半导体衬底共面。 辅助MIM电容器板选择形成在半导体衬底中的STI区域上的下电极或形成在半导体衬底的顶表面中的掺杂阱。 在MIM电容器下板上形成电容器HiK电介质层。 在MIM电容器下板上方的HiK电介质层上形成第二MIM电容器板。

公开(公告)号：US20070262416A1

公开(公告)日：2007-11-15

申请号：US11382544

申请日：2006-05-10

申请人： Ebenezer Eshun ,  Ronald Bolam ,  Douglas Coolbaugh ,  Keith Downes ,  Natalie Feilchenfeld ,  Zhong-Xiang He

发明人： Ebenezer Eshun ,  Ronald Bolam ,  Douglas Coolbaugh ,  Keith Downes ,  Natalie Feilchenfeld ,  Zhong-Xiang He

IPC分类号： H01L29/00

CPC分类号： H01L28/60

摘要： The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

摘要翻译： 本发明涉及一种改进的电容器，其减少边缘缺陷并防止产量失效。 本发明的第一实施例包括与导电层与绝缘体的界面相邻的保护层，而本发明的第二实施例包括位于导电层上的绝缘体上的保护层。

公开(公告)号：US20070155164A1

公开(公告)日：2007-07-05

申请号：US11687017

申请日：2007-03-16

申请人： Steven Barkyoumb ,  Jonathan Chapple-Sokol ,  Edward Cooney ,  Keith Downes ,  Thomas McDevitt ,  William Murphy

发明人： Steven Barkyoumb ,  Jonathan Chapple-Sokol ,  Edward Cooney ,  Keith Downes ,  Thomas McDevitt ,  William Murphy

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76873

摘要： A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.

摘要翻译： 一种用于在半导体结构的制造过程中减少铜籽晶层的腐蚀的方法和结构。 在结构（或包含结构的晶片）离开溅射工具的真空环境之前，将结构加热到高于溅射工具外部环境的水冷凝温度的温度。 结果，当结构离开溅射工具时，水蒸气不会在结构上冷凝，因此防止了水蒸气对种子层的腐蚀。 或者，在结构离开溅射工具环境之前，可以在籽晶层的顶部形成耐水蒸汽的保护层。 在另一替代实施例中，种子层可以包括铜合金（例如用铝），其在暴露于水蒸汽时生长出耐水蒸气的保护层。

公开(公告)号：US20050253265A1

公开(公告)日：2005-11-17

申请号：US10709562

申请日：2004-05-13

申请人： Steven Barkyoumb ,  Jonathan Chapple-Sokol ,  Edward Cooney ,  Keith Downes ,  Thomas McDevitt ,  William Murphy

发明人： Steven Barkyoumb ,  Jonathan Chapple-Sokol ,  Edward Cooney ,  Keith Downes ,  Thomas McDevitt ,  William Murphy

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76859 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76873

摘要： A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.

摘要翻译： 一种用于在半导体结构的制造过程中减少铜籽晶层的腐蚀的方法和结构。 在结构（或包含结构的晶片）离开溅射工具的真空环境之前，将结构加热到高于溅射工具外部环境的水冷凝温度的温度。 结果，当结构离开溅射工具时，水蒸气不会在结构上冷凝，因此防止了水蒸气对种子层的腐蚀。 或者，在结构离开溅射工具环境之前，可以在籽晶层的顶部形成耐水蒸汽的保护层。 在另一替代实施例中，种子层可以包括铜合金（例如用铝），其在暴露于水蒸汽时生长出耐水蒸气的保护层。