Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme
    3.
    发明授权
    Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme 失效
    使用奇数积分方案制造堆叠多晶硅和MOS电容器的方法

    公开(公告)号:US06833299B2

    公开(公告)日:2004-12-21

    申请号:US10292204

    申请日:2002-11-12

    IPC分类号: H01L218244

    CPC分类号: H01L28/40 H01L29/94

    摘要: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

    摘要翻译: 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器,包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层,所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层,所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。

    Poly-poly/MOS capacitor having a gate encapsulating first electrode layer
    4.
    发明授权
    Poly-poly/MOS capacitor having a gate encapsulating first electrode layer 有权
    具有封装了第一电极层的栅极的多晶硅/ MOS电容器

    公开(公告)号:US06507063B2

    公开(公告)日:2003-01-14

    申请号:US09551168

    申请日:2000-04-17

    IPC分类号: H01L27108

    CPC分类号: H01L28/40 H01L29/94

    摘要: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

    摘要翻译: 一种用作BiCMOS器件中的组件的堆叠多晶硅/ MOS电容器,包括在其表面形成有具有第一导电类型的区域的半导体衬底; 形成在覆盖所述第一导电型区域的所述半导体衬底上的栅极氧化物; 形成在至少所述栅极氧化物层上的第一多晶硅层,所述第一多晶硅层掺杂有N或P型掺杂剂; 形成在所述第一多晶硅层上的电介质层; 以及形成在所述介电层上的第二多晶硅层,所述第二多晶硅层掺杂有与所述第一多晶硅层相同或不同的掺杂剂。

    Epitaxial base bipolar transistor with raised extrinsic base
    6.
    发明授权
    Epitaxial base bipolar transistor with raised extrinsic base 有权
    外延基极双极晶体管,外加基极

    公开(公告)号:US06812545B2

    公开(公告)日:2004-11-02

    申请号:US10425270

    申请日:2003-04-29

    IPC分类号: H01L27082

    摘要: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.

    摘要翻译: 一种外延基极双极晶体管,包括在单晶单个衬底上的外延单晶层; 半导体表面上的凸起的发射极; 在半导体衬底的表面上凸起的非本征基底; 凸起的发射极和凸出的外部基极之间的绝缘体,其中所述绝缘体是间隔物; 以及来自凸起的发射极和凸出的外部基极的扩散,以在所述单晶衬底中提供发射极扩散和非本征基极扩散,其中所述发射极扩散具有发射极扩散结深度,并且其中所述发射极延伸到所述衬底表面, 所述基底延伸到所述衬底表面,其中所述发射极与基底表面的高度差小于所述发射极结深度的20%以及其制造方法。