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公开(公告)号:US10134854B2
公开(公告)日:2018-11-20
申请号:US15248676
申请日:2016-08-26
Inventor: Ho Kyun Ahn , Dong Min Kang , Yong-Hwan Kwon , Dong-Young Kim , Seong Il Kim , Hae Cheon Kim , Eun Soo Nam , Jae Won Do , Byoung-Gue Min , Hyung Sup Yoon , Sang-Heung Lee , Jong Min Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
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公开(公告)号:US12166101B2
公开(公告)日:2024-12-10
申请号:US17671171
申请日:2022-02-14
Inventor: Soo Cheol Kang , Hyun Wook Jung , Seong IL Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Il Gyu Choi
IPC: H01L29/66 , H01L29/778
Abstract: A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.
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公开(公告)号:US12131978B2
公开(公告)日:2024-10-29
申请号:US17562587
申请日:2021-12-27
Inventor: Il Gyu Choi , Seong Il Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Hyun Wook Jung
IPC: H01L23/373 , H01L33/64
CPC classification number: H01L23/3738 , H01L23/3731
Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.
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公开(公告)号:US09780176B2
公开(公告)日:2017-10-03
申请号:US15238492
申请日:2016-08-16
Inventor: Jong Min Lee , Byoung-Gue Min , Hyung Sup Yoon , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Hae Cheon Kim , Jae Won Do , Ho Kyun Ahn , Sang-Heung Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho , Chull Won Ju
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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公开(公告)号:US12176306B2
公开(公告)日:2024-12-24
申请号:US17396258
申请日:2021-08-06
Inventor: Sang Heung Lee , Soo Cheol Kang , Seong Il Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Jong Won Lim , Sung Jae Chang , Hyun Wook Jung
IPC: H01L23/64 , H01L29/16 , H01L29/20 , H01L29/205
Abstract: An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.
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公开(公告)号:US09837719B2
公开(公告)日:2017-12-05
申请号:US15229891
申请日:2016-08-05
Inventor: Dong-Young Kim , Dong Min Kang , Seong-Il Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Ho Kyun Ahn , Hyung Sup Yoon , Sang-Heung Lee , Jong Min Lee , Jong-Won Lim , Yoo Jin Jang , Hyun Wook Jung , Kyu Jun Cho , Chull Won Ju
CPC classification number: H01Q9/0407 , H01Q1/50 , H01Q9/0442
Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.
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