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公开(公告)号：US09780176B2
公开(公告)日：2017-10-03
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min Lee , Byoung-Gue Min , Hyung Sup Yoon , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Hae Cheon Kim , Jae Won Do , Ho Kyun Ahn , Sang-Heung Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho , Chull Won Ju
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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公开(公告)号：US09837719B2
公开(公告)日：2017-12-05
申请号：US15229891
申请日：2016-08-05
Inventor： Dong-Young Kim , Dong Min Kang , Seong-Il Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Ho Kyun Ahn , Hyung Sup Yoon , Sang-Heung Lee , Jong Min Lee , Jong-Won Lim , Yoo Jin Jang , Hyun Wook Jung , Kyu Jun Cho , Chull Won Ju
CPC classification number: H01Q9/0407 , H01Q1/50 , H01Q9/0442
Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the multilayered substrate.
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公开(公告)号：US11955961B2
公开(公告)日：2024-04-09
申请号：US17879047
申请日：2022-08-02
Inventor： Hong Gu Ji , Dong Min Kang , Byoung-Gue Min , Jongmin Lee , Kyu Jun Cho
IPC: H03K3/00 , H03K17/687 , H03K17/693
CPC classification number: H03K17/687
Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.
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公开(公告)号：US11817826B2
公开(公告)日：2023-11-14
申请号：US17886061
申请日：2022-08-11
Inventor： Woojin Chang , Dong Min Kang , Byoung-Gue Min , Jong Yul Park , Jongmin Lee , Yoo Jin Jang , Kyu Jun Cho , Hong Gu Ji
Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.
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Patent Agency Ranking
公开(公告)号：US10134854B2
公开(公告)日：2018-11-20
申请号：US15248676
申请日：2016-08-26
Inventor： Ho Kyun Ahn , Dong Min Kang , Yong-Hwan Kwon , Dong-Young Kim , Seong Il Kim , Hae Cheon Kim , Eun Soo Nam , Jae Won Do , Byoung-Gue Min , Hyung Sup Yoon , Sang-Heung Lee , Jong Min Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
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公开(公告)号：US11315951B2
公开(公告)日：2022-04-26
申请号：US17094931
申请日：2020-11-11
Inventor： Sung-Jae Chang , Dong Min Kang , Sung-Bum Bae , Hyung Sup Yoon , Kyu Jun Cho
IPC: H01L27/12 , H01L21/84 , H01L21/683 , H01L23/31
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate having a first region and a second region, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a barrier layer disposed on the semiconductor layer, a first source electrode, a first drain electrode, and a first gate electrode disposed therebetween, which are disposed on the barrier layer in the first region, a second source electrode, a second drain electrode, and a second gate electrode disposed therebetween, which are disposed on the barrier layer in the second region, and a ferroelectric pattern interposed between the first gate electrode and the barrier layer.
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公开(公告)号：US10608102B2
公开(公告)日：2020-03-31
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun Ahn , Min Jeong Shin , Jeong Jin Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Hyung Sup Yoon , Hyung Seok Lee , Jong-Won Lim , Sungjae Chang , Hyunwook Jung , Kyu Jun Cho , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Sang-Heung Lee , Jongmin Lee , Hong Gu Ji
IPC: H01L29/78 , H01L29/45 , H01L29/778 , H01L29/66 , H01L21/3065 , H01L29/417 , H01L29/06 , H01L29/20 , H01L29/423
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
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公开(公告)号：US10256811B2
公开(公告)日：2019-04-09
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin Chang , Jong-Won Lim , Dong Min Kang , Dong-Young Kim , Seong-il Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Min Jeong Shin , Hokyun Ahn , Hyung Sup Yoon , Sang-Heung Lee , Jongmin Lee , Sungjae Chang , Yoo Jin Jang , Hyunwook Jung , Kyu Jun Cho , Hong Gu Ji
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353 , H03K17/0812 , H03K17/10 , H03K17/12 , H03K17/14 , H03K17/16 , H03K17/28
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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公开(公告)号：US09899226B2
公开(公告)日：2018-02-20
申请号：US14658121
申请日：2015-03-13
Inventor： Ho Kyun Ahn , Hae Cheon Kim , Jong Won Lim , Dong Min Kang , Yong Hwan Kwon , Seong Il Kim , Zin Sig Kim , Eun Soo Nam , Byoung Gue Min , Hyung Sup Yoon , Kyung Ho Lee , Jong Min Lee , Kyu Jun Cho
IPC: H01L29/40 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/51 , H01L29/20 , H01L29/45
CPC classification number: H01L21/28264 , H01L29/2003 , H01L29/407 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
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