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公开(公告)号：US12166101B2
公开(公告)日：2024-12-10
申请号：US17671171
申请日：2022-02-14
Inventor： Soo Cheol Kang , Hyun Wook Jung , Seong IL Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Il Gyu Choi
IPC: H01L29/66 , H01L29/778
Abstract: A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.
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2.发明授权公开(公告)号：US09438199B2
公开(公告)日：2016-09-06
申请号：US14478295
申请日：2014-09-05
Inventor： Dong Min Kang , Seong Il Kim , Sang Heung Lee , Chull Won Ju , Ho Kyun Ahn , Hyung Sup Yoon , Jong Won Lim
CPC classification number: H03H7/38 , H01L23/642 , H01L2224/49175 , H01P1/2039 , H01P5/12 , H05K1/025 , H05K2201/09781
Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.
Abstract translation: 本文提供了一种包括匹配单元及其匹配方法的组件封装，所述匹配单元包括：衬底; 形成在所述基板上的传输线，所述传输线连接到所述部件封装的端子; 电连接所述传输线和中心部件的接合线; 以及具有通过布线连接与传输线电连接的多个电容器的电容器单元，其中匹配单元的电感通过调整接合线的长度而变化，并且匹配单元的电容可通过增加或减小而变化 通过延长或切断布线连接，在电容器单元内的电容器之间电连接到传输线的电容器的数量。
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公开(公告)号：US10134854B2
公开(公告)日：2018-11-20
申请号：US15248676
申请日：2016-08-26
Inventor： Ho Kyun Ahn , Dong Min Kang , Yong-Hwan Kwon , Dong-Young Kim , Seong Il Kim , Hae Cheon Kim , Eun Soo Nam , Jae Won Do , Byoung-Gue Min , Hyung Sup Yoon , Sang-Heung Lee , Jong Min Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
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公开(公告)号：US09537458B2
公开(公告)日：2017-01-03
申请号：US14666163
申请日：2015-03-23
Inventor： Sang Heung Lee , Dong Min Kang , Seong Il Kim , Ho Kyun Ahn , Hyung Sup Yoon , Jong Won Lim , Chull Won Ju
CPC classification number: H03G1/0088 , H03F1/083 , H03F3/08 , H03F2200/153 , H03G3/12
Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.
Abstract translation: 本文提供了一种反馈放大器，包括：放大器电路，被配置为放大从输入端输入的输入信号，并将放大的输入信号输出到输出端; 反馈电路，被配置为向输出端子输出的信号施加反馈电阻值，并且通过利用所确定的反馈电阻值施加的偏置电压来调节所述输入信号来控制所述放大器电路的增益; 分组信号传感器，被配置为通过比较来自所述输出端子的输出与最小信号电平之间的比较，产生用于控制所述反馈电阻值中包括的固定电阻值的固定电阻控制信号; 以及固定电阻控制器，其被配置为响应于所述固定电阻控制信号来控制包括在所述反馈电阻值中的所述固定电阻值。
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5.发明授权Semiconductor device having stable gate structure and method of manufacturing the same 有权具有稳定栅极结构的半导体器件及其制造方法公开(公告)号：US09166011B2
公开(公告)日：2015-10-20
申请号：US14328247
申请日：2014-07-10
Inventor： Seong Il Kim , Dong Min Kang , Sang Heung Lee , Ho Kyun Ahn , Hyung Sup Yoon , Byoung Gue Min , Jong Won Lim
IPC: H01L21/338 , H01L29/423 , H01L29/778 , H01L21/283 , H01L21/28
CPC classification number: H01L29/42312 , H01L21/28114 , H01L21/28587 , H01L21/28593 , H01L29/42316 , H01L29/66863 , H01L29/778 , H01L29/812
Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.
Abstract translation: 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。
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Patent Agency Ranking
6.发明授权Wafer level packaged GaN power semiconductor device and the manufacturing method thereof 有权晶圆级封装GaN功率半导体器件及其制造方法公开(公告)号：US09012920B2
公开(公告)日：2015-04-21
申请号：US13867328
申请日：2013-04-22
Inventor： Chull Won Ju , Hae Cheon Kim , Hyung Sup Yoon , Woo Jin Chang , Sang-Heung Lee , Dong-Young Kim , Jong-Won Lim , Dong Min Kang , Ho Kyun Ahn , Jong Min Lee , Eun Soo Nam
IPC: H01L29/20 , H01L29/66 , H01L29/417 , H01L29/778 , H01L23/00
CPC classification number: H01L29/2003 , H01L24/05 , H01L24/06 , H01L24/16 , H01L29/41758 , H01L29/66431 , H01L29/66462 , H01L29/7787 , H01L2224/0401 , H01L2224/05554 , H01L2224/05568 , H01L2224/056 , H01L2224/06135 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/00014
Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded. By this configuration, it is possible to reduce the process costs by forming the bump on the substrate based on the wafer level, rapidly emit the heat generated from an AlGaN HEMT device by forming the sub source contact pad and the sub drain contact pad of the substrate in the active region, and efficiently emit the heat generated from the AlGaN HEMT device by forming a via hole on the substrate and filling the via hole with the conductive metal.
Abstract translation: 公开了一种GaN（氮化镓）复合功率半导体器件及其制造方法。 氮化镓化合物功率半导体器件包括：通过在晶片上生长形成的氮化镓复合元素; 包括源极，漏极和与氮化镓复合元件连接的栅极的接触焊盘; 将氮化镓化合物元件倒装芯片接合的模块基板; 形成在所述模块基板上的焊盘; 以及形成在模块基板的焊盘上的凸点，使得接触焊盘和焊盘被倒装芯片接合。 通过这种结构，可以通过基于晶片级在基板上形成凸块来降低处理成本，通过形成子源接触焊盘和子漏极接触焊盘，快速地发射由AlGaN HEMT器件产生的热量 衬底，并且通过在衬底上形成通孔并用导电金属填充通孔，从而有效地发射由AlGaN HEMT器件产生的热量。
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公开(公告)号：US09899226B2
公开(公告)日：2018-02-20
申请号：US14658121
申请日：2015-03-13
Inventor： Ho Kyun Ahn , Hae Cheon Kim , Jong Won Lim , Dong Min Kang , Yong Hwan Kwon , Seong Il Kim , Zin Sig Kim , Eun Soo Nam , Byoung Gue Min , Hyung Sup Yoon , Kyung Ho Lee , Jong Min Lee , Kyu Jun Cho
IPC: H01L29/40 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/51 , H01L29/20 , H01L29/45
CPC classification number: H01L21/28264 , H01L29/2003 , H01L29/407 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
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公开(公告)号：US12131978B2
公开(公告)日：2024-10-29
申请号：US17562587
申请日：2021-12-27
Inventor： Il Gyu Choi , Seong Il Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Hyun Wook Jung
IPC: H01L23/373 , H01L33/64
CPC classification number: H01L23/3738 , H01L23/3731
Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.
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公开(公告)号：US09780176B2
公开(公告)日：2017-10-03
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min Lee , Byoung-Gue Min , Hyung Sup Yoon , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Hae Cheon Kim , Jae Won Do , Ho Kyun Ahn , Sang-Heung Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho , Chull Won Ju
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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公开(公告)号：US09209266B2
公开(公告)日：2015-12-08
申请号：US14555182
申请日：2014-11-26
Inventor： Jong-Won Lim , Ho Kyun Ahn , Young Rak Park , Dong Min Kang , Woo Jin Chang , Seong-il Kim , Sung Bum Bae , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/265 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/423 , H01L29/778 , H01L29/16 , H01L21/311
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。
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