-
公开(公告)号：US09899226B2
公开(公告)日：2018-02-20
申请号：US14658121
申请日：2015-03-13
Inventor： Ho Kyun Ahn , Hae Cheon Kim , Jong Won Lim , Dong Min Kang , Yong Hwan Kwon , Seong Il Kim , Zin Sig Kim , Eun Soo Nam , Byoung Gue Min , Hyung Sup Yoon , Kyung Ho Lee , Jong Min Lee , Kyu Jun Cho
IPC: H01L29/40 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/51 , H01L29/20 , H01L29/45
CPC classification number: H01L21/28264 , H01L29/2003 , H01L29/407 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
-
公开(公告)号：US12131978B2
公开(公告)日：2024-10-29
申请号：US17562587
申请日：2021-12-27
Inventor： Il Gyu Choi , Seong Il Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Hyun Wook Jung
IPC: H01L23/373 , H01L33/64
CPC classification number: H01L23/3738 , H01L23/3731
Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.
-
3.发明授权GaN transistor with improved bonding pad structure and method of fabricating the same 有权具有改进的焊盘结构的GaN晶体管及其制造方法公开(公告)号：US09165896B2
公开(公告)日：2015-10-20
申请号：US14453969
申请日：2014-08-07
Inventor： Hae Cheon Kim , Ho Kyun Ahn , Byoung Gue Min , Hyung Sup Yoon , Jong Won Lim
CPC classification number: H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0225 , H01L2224/03466 , H01L2224/03848 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/48463 , H01L2924/00014 , H01L2924/10158 , H01L2924/1033 , H01L2924/1304 , H01L2924/13091 , H01L2924/1423 , H01L2924/201 , H01L2924/37001 , H01L2224/45099
Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.
Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。
-
Patent Agency Ranking
公开(公告)号：US09537458B2
公开(公告)日：2017-01-03
申请号：US14666163
申请日：2015-03-23
Inventor： Sang Heung Lee , Dong Min Kang , Seong Il Kim , Ho Kyun Ahn , Hyung Sup Yoon , Jong Won Lim , Chull Won Ju
CPC classification number: H03G1/0088 , H03F1/083 , H03F3/08 , H03F2200/153 , H03G3/12
Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.
Abstract translation: 本文提供了一种反馈放大器，包括：放大器电路，被配置为放大从输入端输入的输入信号，并将放大的输入信号输出到输出端; 反馈电路，被配置为向输出端子输出的信号施加反馈电阻值，并且通过利用所确定的反馈电阻值施加的偏置电压来调节所述输入信号来控制所述放大器电路的增益; 分组信号传感器，被配置为通过比较来自所述输出端子的输出与最小信号电平之间的比较，产生用于控制所述反馈电阻值中包括的固定电阻值的固定电阻控制信号; 以及固定电阻控制器，其被配置为响应于所述固定电阻控制信号来控制包括在所述反馈电阻值中的所述固定电阻值。
-
5.发明授权Semiconductor device having stable gate structure and method of manufacturing the same 有权具有稳定栅极结构的半导体器件及其制造方法公开(公告)号：US09166011B2
公开(公告)日：2015-10-20
申请号：US14328247
申请日：2014-07-10
Inventor： Seong Il Kim , Dong Min Kang , Sang Heung Lee , Ho Kyun Ahn , Hyung Sup Yoon , Byoung Gue Min , Jong Won Lim
IPC: H01L21/338 , H01L29/423 , H01L29/778 , H01L21/283 , H01L21/28
CPC classification number: H01L29/42312 , H01L21/28114 , H01L21/28587 , H01L21/28593 , H01L29/42316 , H01L29/66863 , H01L29/778 , H01L29/812
Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 μm or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.
Abstract translation: 公开了一种具有稳定的栅极结构的半导体器件及其制造方法，其中通过在栅极头的宽度方向上的栅极头附近还包括多个栅极脚来稳定栅极结构，以作为支撑体 在包括具有0.2μm或更小的长度的精细栅极脚的栅极结构中，并且栅极头具有预定尺寸。 因此，可以防止半导体器件的栅电极塌陷，并且在半导体器件的处理期间或之后提高半导体器件的可靠性。
-
公开(公告)号：US12176306B2
公开(公告)日：2024-12-24
申请号：US17396258
申请日：2021-08-06
Inventor： Sang Heung Lee , Soo Cheol Kang , Seong Il Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Jong Won Lim , Sung Jae Chang , Hyun Wook Jung
IPC: H01L23/64 , H01L29/16 , H01L29/20 , H01L29/205
Abstract: An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.
-
公开(公告)号：US12166101B2
公开(公告)日：2024-12-10
申请号：US17671171
申请日：2022-02-14
Inventor： Soo Cheol Kang , Hyun Wook Jung , Seong IL Kim , Hae Cheon Kim , Youn Sub Noh , Ho Kyun Ahn , Sang Heung Lee , Jong Won Lim , Sung Jae Chang , Il Gyu Choi
IPC: H01L29/66 , H01L29/778
Abstract: A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.
-
8.发明授权公开(公告)号：US09438199B2
公开(公告)日：2016-09-06
申请号：US14478295
申请日：2014-09-05
Inventor： Dong Min Kang , Seong Il Kim , Sang Heung Lee , Chull Won Ju , Ho Kyun Ahn , Hyung Sup Yoon , Jong Won Lim
CPC classification number: H03H7/38 , H01L23/642 , H01L2224/49175 , H01P1/2039 , H01P5/12 , H05K1/025 , H05K2201/09781
Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.
Abstract translation: 本文提供了一种包括匹配单元及其匹配方法的组件封装，所述匹配单元包括：衬底; 形成在所述基板上的传输线，所述传输线连接到所述部件封装的端子; 电连接所述传输线和中心部件的接合线; 以及具有通过布线连接与传输线电连接的多个电容器的电容器单元，其中匹配单元的电感通过调整接合线的长度而变化，并且匹配单元的电容可通过增加或减小而变化 通过延长或切断布线连接，在电容器单元内的电容器之间电连接到传输线的电容器的数量。
-
-
-
-
-
-
-
Search Results
8
records
(took 0.23 seconds)
