-
公开(公告)号：US10608102B2
公开(公告)日：2020-03-31
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun Ahn , Min Jeong Shin , Jeong Jin Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Hyung Sup Yoon , Hyung Seok Lee , Jong-Won Lim , Sungjae Chang , Hyunwook Jung , Kyu Jun Cho , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Sang-Heung Lee , Jongmin Lee , Hong Gu Ji
IPC: H01L29/78 , H01L29/45 , H01L29/778 , H01L29/66 , H01L21/3065 , H01L29/417 , H01L29/06 , H01L29/20 , H01L29/423
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
-
公开(公告)号：US09224830B2
公开(公告)日：2015-12-29
申请号：US13914713
申请日：2013-06-11
Inventor： Seong-Il Kim , Jong-Won Lim , Dong Min Kang , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Byoung-Gue Min , Jongmin Lee , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/812 , H01L29/66 , H01L29/40 , H01L29/41 , H01L29/423 , H01L29/778 , H01L29/16 , H01L29/20
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.
Abstract translation: 提供场效应晶体管。 晶体管可以包括在基板上彼此间隔开设置的源电极和漏电极，以及设置在位于源极和漏极之间的基板的一部分上的“+”形栅电极。
-
公开(公告)号：US08901608B2
公开(公告)日：2014-12-02
申请号：US13908076
申请日：2013-06-03
Inventor： Jong-Won Lim , Hokyun Ahn , Woojin Chang , Dong Min Kang , Seong-Il Kim , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L33/00 , H01L29/66 , H01L29/778
CPC classification number: H01L29/778 , H01L29/402 , H01L29/42316 , H01L29/66431
Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.
Abstract translation: 高电子迁移率晶体管包括设置在源极和漏极之间的衬底上的T型栅电极和设置在衬底和T型栅电极之间的绝缘层。 绝缘层包括第一绝缘层，第二绝缘层和第三绝缘层。 第三绝缘层设置在基板和T型栅电极的头部之间，使得第三绝缘层的一部分与T型栅极的脚部接触。 第二绝缘层设置在基板与T型栅电极的头部之间以与第三绝缘层接触。 所述第一绝缘层和所述第三绝缘层的另一部分依次层叠在所述基板与所述T型栅电极的头部之间，以与所述第二绝缘层接触。
-
公开(公告)号：US11223333B2
公开(公告)日：2022-01-11
申请号：US16941691
申请日：2020-07-29
Inventor： Woojin Chang , Seong-Il Kim , Sang-Heung Lee , Jongmin Lee
Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.
-
公开(公告)号：US09634112B2
公开(公告)日：2017-04-25
申请号：US14633984
申请日：2015-02-27
Inventor： Hyung Sup Yoon , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Seong-Il Kim , Sang Heung Lee , Dong Min Kang , Chull Won Ju , Jae Kyoung Mun
IPC: H01L29/66 , H01L29/778 , H01L29/40 , H01L29/423 , H01L29/20 , H01L21/02 , H01L21/28 , H01L21/311 , H01L29/201 , H01L29/205 , H01L21/285
CPC classification number: H01L29/66462 , H01L21/02118 , H01L21/0217 , H01L21/02178 , H01L21/0254 , H01L21/28264 , H01L21/28593 , H01L21/31111 , H01L21/31144 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/404 , H01L29/42316 , H01L29/42376 , H01L29/778 , H01L29/7786
Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.
-
Patent Agency Ranking
公开(公告)号：US08841969B2
公开(公告)日：2014-09-23
申请号：US13670016
申请日：2012-11-06
Inventor： Sang-Heung Lee , Seong-Il Kim , Dong Min Kang , Jong-Won Lim , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H03G3/12
CPC classification number: H03G1/0082 , H03G1/0088 , H03G3/3084
Abstract: Disclosed is an automatic gain control feedback amplifier that can arbitrarily control a gain even when a difference in input signal is large. The automatic gain control feedback amplifier includes: an amplification circuit unit configured to amplify voltage input from an input terminal and output the amplified voltage to an output terminal; a feedback circuit unit connected between the input terminal and the output terminal and including a feedback resistor unit of which a total resistance value is determined by one or more control signals and a feedback transistor connected to the feedback resistor unit in parallel; and a bias circuit unit configured to supply predetermined bias voltage to the feedback transistor.
Abstract translation: 公开了一种自动增益控制反馈放大器，其即使当输入信号的差异大时也可以任意地控制增益。 自动增益控制反馈放大器包括：放大电路单元，被配置为放大从输入端输入的电压，并将放大的电压输出到输出端; 连接在输入端子和输出端子之间的反馈电路单元，包括反馈电阻器单元，其总电阻值由一个或多个控制信号确定，反馈晶体管并联连接到反馈电阻器单元; 以及偏置电路单元，被配置为向所述反馈晶体管提供预定的偏置电压。
-
公开(公告)号：US20140160689A1
公开(公告)日：2014-06-12
申请号：US13959666
申请日：2013-08-05
Inventor： Dong Min KANG , Chull Won Ju , Seong-Il Kim , Sang-Heung Lee , Jong-Won Lim , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
IPC: H05K1/02
CPC classification number: H01L23/66 , H01L23/49844 , H01L2223/6655 , H01L2224/48091 , H01L2224/49175 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
Abstract: A package includes a ground plate, a chip mounting plate disposed at a side of the ground plate and having a top surface lower than a top surface of the ground plate, a chip on the chip mounting plate, a first input/output terminal opposite to the chip mounting plate and disposed at another side of the ground plate, and a second input/output terminal opposite to the ground plate and disposed at a side of the chip mounting plate. The first and second input/output terminals are electrically connected to the chip.
Abstract translation: 一种封装，包括接地板，设置在接地板一侧的芯片安装板，具有比接地板的顶表面低的顶表面，芯片安装板上的芯片，与第一输入/输出端子相对的第一输入/输出端子 芯片安装板并且设置在接地板的另一侧，以及与接地板相对的第二输入/输出端子，并且设置在芯片安装板的一侧。 第一和第二输入/输出端子与芯片电连接。
-
8.发明申请IMPEDANCE MATCHING CIRCUIT, POWER AMPLIFIER AND MANUFACTURING METHOD FOR VARIABLE CAPACITOR 审中-公开阻抗匹配电路，功率放大器和可变电容器的制造方法公开(公告)号：US20130207730A1
公开(公告)日：2013-08-15
申请号：US13743667
申请日：2013-01-17
Inventor： Jongmin LEE , Byoung-Gue Min , Seong-Il Kim , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H01L21/8222 , H01G7/00 , H01L27/0647 , H01L27/0658 , H01L29/93 , H03F1/565 , H03F3/21 , H03F2200/36 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03H7/38 , Y10T29/43
Abstract: Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.
Abstract translation: 公开了能够进行宽带匹配的阻抗匹配电路。 阻抗匹配电路包括：第一可变电感器单元，其一端连接到第一节点，电感值变化; 连接在第一节点和第二节点之间并具有可变电感值的第二电感器单元; 第一可变电容器单元，其一端连接到第一节点，电容值变化; 以及第二可变电容器单元，其一端连接到第二节点并且电容值变化，并且第一可变电容器单元的另一端和第二可变电容器单元的另一端连接到接地电压端子 执行连接到第一可变电感器单元的另一端的电路与连接到第二节点的电路之间的阻抗匹配。
-
公开(公告)号：US09780176B2
公开(公告)日：2017-10-03
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min Lee , Byoung-Gue Min , Hyung Sup Yoon , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Hae Cheon Kim , Jae Won Do , Ho Kyun Ahn , Sang-Heung Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho , Chull Won Ju
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
-
公开(公告)号：US20150171188A1
公开(公告)日：2015-06-18
申请号：US14633984
申请日：2015-02-27
Inventor： Hyung Sup YOON , Byoung-Gue MIN , Jong-Won LIM , Hokyun AHN , Seong-Il Kim , Sang Heung LEE , Dong Min KANG , Chull Won JU , Jae Kyoung MUN
IPC: H01L29/66 , H01L29/201 , H01L21/02 , H01L21/28 , H01L21/311 , H01L29/423 , H01L29/20 , H01L29/205
CPC classification number: H01L29/66462 , H01L21/02118 , H01L21/0217 , H01L21/02178 , H01L21/0254 , H01L21/28264 , H01L21/28593 , H01L21/31111 , H01L21/31144 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/404 , H01L29/42316 , H01L29/42376 , H01L29/778 , H01L29/7786
Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.
Abstract translation: 提供场效应晶体管。 场效应晶体管可以包括衬底上的覆盖层，覆盖层上的源欧姆电极和漏极欧姆电极，堆叠在覆盖层上以覆盖源极和漏极欧姆电极的第一绝缘层和第二绝缘层， 包括脚部和头部的栅格电极，所述脚部分连接到所述源欧姆电极和所述漏极欧姆电极之间的衬底，并且所述头部从所述腿部延伸以覆盖所述源极欧姆电极和所述漏极欧姆电极的顶表面 所述第二绝缘层，在所述第二绝缘层上覆盖所述栅格电极的第一平坦化层和所述第一平坦化层上的第一电极，所述第一电极连接到所述源欧姆电极或所述漏极欧姆电极。
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.016 seconds)
