公开(公告)号：US08780643B2

公开(公告)日：2014-07-15

申请号：US13924033

申请日：2013-06-21

Applicant: Elpida Memory, Inc.

Inventor： Toru Ishikawa

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1066 ,  G11C7/22

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

Abstract translation: 存储器系统包括具有共同连接到存储器控制器的数据端的多个存储器件。 每个存储器件包括数据输出电路，该数据输出电路响应于对数据端子的读取命令而输出从存储器单元阵列读取的读取数据;以及输出定时调整电路，其调整读取数据的输出定时， 从数据输出电路输出。 存储器控制器设置由输出定时调整电路执行的调整调整量，使得从读取命令发出到接收到读取数据的延迟时间在存储器件中匹配时，通过向每个 存储设备。

公开(公告)号：US20130283001A1

公开(公告)日：2013-10-24

申请号：US13844918

申请日：2013-03-16

Applicant: ELPIDA MEMORY, INC.

Inventor： Toru Ishikawa

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1018 ,  G11C11/4076

Abstract: Disclosed herein is a device that includes: a data terminal; a plurality of memory banks; and a control circuit configured to control a data transfer between the data terminal and the memory banks. The control circuit is configured to set a read latency in response to a burst length.

Abstract translation: 本文公开了一种设备，包括：数据终端; 多个存储体; 以及控制电路，被配置为控制数据终端和存储体之间的数据传输。 控制电路被配置为响应于突发长度来设置读延迟。

公开(公告)号：US08957695B2

公开(公告)日：2015-02-17

申请号：US13720863

申请日：2012-12-19

Applicant: Elpida Memory, Inc.

Inventor： Tetsuji Takahashi ,  Toru Ishikawa

IPC: H01L21/66 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L22/34 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05552

Abstract: Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal.

Abstract translation: 这里公开了一种装置，其包括：外部端子; 第一芯片，包括产生第一控制信号的第一控制电路; 以及与第一芯片堆叠的第二芯片。 第二芯片包括：第一测试端子，其被提供有第一测试信号并且不与任何一个外部端子连接; 提供有第一测试信号并耦合到外部端子之一的第二测试终端，而不连接到第一芯片的任何一个控制电路; 第一正常端子，被提供有第一控制信号并且通过第一芯片的第一控制电路的介入耦合到另一个外部端子; 以及第一选择电路，包括共同耦合到第一和第二测试终端的第一输入节点和耦合到第一正常终端的第二输入节点。

公开(公告)号：US08665653B2

公开(公告)日：2014-03-04

申请号：US13924055

申请日：2013-06-21

Applicant: Elpida Memory, Inc.

Inventor： Toru Ishikawa

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1066 ,  G11C7/22

Abstract: A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices.

公开(公告)号：US20140002144A1

公开(公告)日：2014-01-02

申请号：US14018784

申请日：2013-09-05

Applicant: Elpida Memory, Inc.

Inventor： Toru HATAKEYAMA ,  Toru Ishikawa

IPC: H03K19/00

CPC classification number: H03K19/0027 ,  G11C5/06 ,  G11C7/1087

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract translation: 半导体器件包括调整逻辑阈值电压的第一输入缓冲器，第一复制电路，第一参考电压产生电路和第一比较器电路。 第一复制电路在电路配置与第一输入缓冲器相同。 第一个复制电路具有连接到输入的输入和输出。 第一个复制电路产生逻辑阈值电压作为输出电压。 第一参考电压产生电路产生第一参考电压。 第一比较器电路将逻辑阈值电压作为第一复制电路的输出电压与第一参考电压进行比较，以产生第一阈值调整信号。 第一比较器电路将第一阈值调整信号提供给第一输入缓冲器和第一复制电路。 第一阈值调整信号允许第一输入缓冲器调整逻辑阈值电压。

公开(公告)号：US20130114364A1

公开(公告)日：2013-05-09

申请号：US13670802

申请日：2012-11-07

Applicant: Elpida Memory, Inc.

Inventor： Kenichi SAKAKIBARA ,  Toru Ishikawa

IPC: G11C11/402

CPC classification number: G11C11/40626 ,  G11C11/40618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.

公开(公告)号：US08994401B2

公开(公告)日：2015-03-31

申请号：US14018784

申请日：2013-09-05

Applicant: Elpida Memory, Inc.

Inventor： Toru Hatakeyama ,  Toru Ishikawa

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K19/0027 ,  G11C5/06 ,  G11C7/1087

Abstract: A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

Abstract translation: 半导体器件包括调整逻辑阈值电压的第一输入缓冲器，第一复制电路，第一参考电压产生电路和第一比较器电路。 第一复制电路在电路配置与第一输入缓冲器相同。 第一个复制电路具有连接到输入的输入和输出。 第一个复制电路产生逻辑阈值电压作为输出电压。 第一参考电压产生电路产生第一参考电压。 第一比较器电路将逻辑阈值电压作为第一复制电路的输出电压与第一参考电压进行比较，以产生第一阈值调整信号。 第一比较器电路将第一阈值调整信号提供给第一输入缓冲器和第一复制电路。 第一阈值调整信号允许第一输入缓冲器调整逻辑阈值电压。

公开(公告)号：US08873325B2

公开(公告)日：2014-10-28

申请号：US13670802

申请日：2012-11-07

Applicant: Elpida Memory, Inc.

Inventor： Kenichi Sakakibara ,  Toru Ishikawa

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/40618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.

Abstract translation: 本文公开了包括第一半导体芯片的装置。 第一半导体芯片包括存储数据的第一数据存储区域，对第一数据存储区域重复第一刷新操作以使第一数据存储区域保留数据的第一刷新电路，从外部提供第一控制信号的第一终端 以及耦合在所述第一端子和所述第一刷新电路之间的第一控制电路，以响应于所述第一控制信号来控制所述第一刷新操作的重复周期。

公开(公告)号：US20130227229A1

公开(公告)日：2013-08-29

申请号：US13773502

申请日：2013-02-21

Applicant: Elpida Memory, Inc.

Inventor： Toru Ishikawa

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F12/023 ,  G06F12/0607 ,  G06F12/0879 ,  G06F13/1647 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/1042 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A semiconductor device includes a command terminal, a plurality of memory banks, a control circuit and an output circuit. The control circuit is configured to respond to each of issuance of a read command, that is supplied to the command terminal, to perform a read operation on any one of the memory banks so that the any one of the memory banks output a plurality of read data sets. The output circuit receives the read data sets and outputs the read data sets to outside in response to a clock signal so that a first interval substantially the same as a period of the clock signal or longer than the period of the clock signal is interposed between the read data sets.

Abstract translation: 半导体器件包括命令终端，多个存储体，控制电路和输出电路。 控制电路被配置为响应于提供给命令终端的读取命令的每个发出，以对存储器组中的任何一个执行读取操作，使得存储器组中的任何一个输出多个读取 数据集。 输出电路接收读数据组并响应于时钟信号将读数据组输出到外部，使得与时钟信号的周期基本相同或长于时钟信号的周期的第一间隔插入在 读取数据集。