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公开(公告)号：US20090172344A1
公开(公告)日：2009-07-02
申请号：US11967868
申请日：2007-12-31
申请人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
摘要翻译： 方法，系统和装置可以对存储器中固定的多个页面的固定的多个页表条目进行初始化，每个页面具有第一大小，其中每个页表条目的线性地址对应于物理地址，固定多个 的页面对齐。 可以将针对对齐的页面的每个页表条目中的一个位设置为指示固定的多个页面是否被视为具有大于第一页面大小的第二页面大小的一个组合页面。 描述和要求保护其他实施例。
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公开(公告)号：US09244855B2
公开(公告)日：2016-01-26
申请号：US11967868
申请日：2007-12-31
申请人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
摘要翻译： 方法，系统和装置可以对存储器中固定的多个页面的固定的多个页表条目进行初始化，每个页面具有第一大小，其中每个页表条目的线性地址对应于物理地址，固定多个 的页面对齐。 可以将针对对齐的页面的每个页表条目中的一个位设置为指示固定的多个页面是否被视为具有大于第一页面大小的第二页面大小的一个组合页面。 描述和要求保护其他实施例。
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公开(公告)号：US20170192904A1
公开(公告)日：2017-07-06
申请号：US15384067
申请日：2016-12-19
申请人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/1009 , G06F12/109 , G06F12/1027
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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公开(公告)号：US20130117531A1
公开(公告)日：2013-05-09
申请号：US13722485
申请日：2012-12-20
申请人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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公开(公告)号：US20170199825A1
公开(公告)日：2017-07-13
申请号：US15384054
申请日：2016-12-19
申请人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Edward Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/1009 , G06F12/14 , G06F12/0864 , G06F12/1027
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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公开(公告)号：US20160179533A1
公开(公告)日：2016-06-23
申请号：US14581285
申请日：2014-12-23
申请人： Roger Gramunt , Rammohan Padmanabhan , Ramon Matas , Neal S. Moyer , Benjamin C. Chaffin , Avinash Sodani , Alexey P. Suprun , Vikram S. Sundaram , Chung-Lun Chan , Gerardo A. Fernandez , Julio Gago , Michael S. Yang , Aditya Kesiraju
发明人： Roger Gramunt , Rammohan Padmanabhan , Ramon Matas , Neal S. Moyer , Benjamin C. Chaffin , Avinash Sodani , Alexey P. Suprun , Vikram S. Sundaram , Chung-Lun Chan , Gerardo A. Fernandez , Julio Gago , Michael S. Yang , Aditya Kesiraju
CPC分类号： G06F12/122 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3859 , G06F9/4806 , G06F2212/62
摘要： In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.
摘要翻译： 在一个实施例中，处理器包括前端单元，前端单元具有用于接收和解码多个线程的指令的指令解码器，耦合到指令解码器以接收和执行解码指令的执行单元，以及退休指令 从执行单元接收指令并且退出与具有等待退休的指令或事件的一个或多个线程相关联的指令的逻辑。 指令退出单元包括线程仲裁逻辑，用于一次选择一个线程，并将所选线程发送到用于退出处理的退出逻辑。
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公开(公告)号：US07627735B2
公开(公告)日：2009-12-01
申请号：US11255676
申请日：2005-10-21
申请人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
发明人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
IPC分类号： G06F15/16
CPC分类号： G06F12/1027 , G06F12/0844 , Y02D10/13
摘要： In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有用于存储矢量数据的寄存器文件的装置，耦合到寄存器文件以产生矢量存储器操作的地址的地址发生器，以及控制器，用于从一个或多个片段生成输出片段 包括多个地址，其中输出切片包括各自对应于存储器的单独可寻址部分的地址。 描述和要求保护其他实施例。
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公开(公告)号：US08316216B2
公开(公告)日：2012-11-20
申请号：US12582829
申请日：2009-10-21
申请人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
发明人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
IPC分类号： G06F15/16
CPC分类号： G06F12/1027 , G06F12/0844 , Y02D10/13
摘要： In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有用于存储矢量数据的寄存器文件的装置，耦合到寄存器文件以产生矢量存储器操作的地址的地址发生器，以及控制器，用于从一个或多个片段生成输出片段 包括多个地址，其中输出切片包括各自对应于存储器的单独可寻址部分的地址。 描述和要求保护其他实施例。
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公开(公告)号：US20070094477A1
公开(公告)日：2007-04-26
申请号：US11255676
申请日：2005-10-21
申请人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
发明人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0844 , Y02D10/13
摘要： In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有用于存储矢量数据的寄存器文件的装置，耦合到寄存器文件以产生矢量存储器操作的地址的地址发生器，以及控制器，用于从一个或多个片段生成输出片段 包括多个地址，其中输出切片包括各自对应于存储器的单独可寻址部分的地址。 描述和要求保护其他实施例。
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公开(公告)号：US08707012B2
公开(公告)日：2014-04-22
申请号：US13650403
申请日：2012-10-12
申请人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
发明人： Roger Espasa , Joel Emer , Geoff Lowney , Roger Gramunt , Santiago Galan , Toni Juan , Jesus Corbal , Federico Ardanaz , Isaac Hernandez
IPC分类号： G06F15/16
CPC分类号： G06F12/1027 , G06F12/0844 , Y02D10/13
摘要： In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有用于存储矢量数据的寄存器文件的装置，耦合到寄存器文件以产生矢量存储器操作的地址的地址发生器，以及控制器，用于从一个或多个片段生成输出片段 包括多个地址，其中输出切片包括各自对应于存储器的单独可寻址部分的地址。 描述和要求保护其他实施例。
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