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公开(公告)号：US20090172344A1
公开(公告)日：2009-07-02
申请号：US11967868
申请日：2007-12-31
申请人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
摘要翻译： 方法，系统和装置可以对存储器中固定的多个页面的固定的多个页表条目进行初始化，每个页面具有第一大小，其中每个页表条目的线性地址对应于物理地址，固定多个 的页面对齐。 可以将针对对齐的页面的每个页表条目中的一个位设置为指示固定的多个页面是否被视为具有大于第一页面大小的第二页面大小的一个组合页面。 描述和要求保护其他实施例。
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公开(公告)号：US09244855B2
公开(公告)日：2016-01-26
申请号：US11967868
申请日：2007-12-31
申请人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
发明人： Ed Grochowski , Julio Gago , Roger Gramunt , Roger Espasa , Rolf Kassa
CPC分类号： G06F12/1009 , G06F12/0864 , G06F12/1027 , G06F12/109 , G06F12/145 , G06F2212/152 , G06F2212/6032 , G06F2212/652 , G06F2212/657 , G06F2212/68
摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
摘要翻译： 方法，系统和装置可以对存储器中固定的多个页面的固定的多个页表条目进行初始化，每个页面具有第一大小，其中每个页表条目的线性地址对应于物理地址，固定多个 的页面对齐。 可以将针对对齐的页面的每个页表条目中的一个位设置为指示固定的多个页面是否被视为具有大于第一页面大小的第二页面大小的一个组合页面。 描述和要求保护其他实施例。
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3.发明授权公开(公告)号：US09720697B2
公开(公告)日：2017-08-01
申请号：US13608970
申请日：2012-09-10
申请人： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
发明人： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
CPC分类号： G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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4.发明授权Load balancing for multi-threaded applications via asymmetric power throttling 有权通过不对称功率节流对多线程应用进行负载平衡公开(公告)号：US08108863B2
公开(公告)日：2012-01-31
申请号：US11322823
申请日：2005-12-30
申请人： Ryan Rakvic , Richard A. Hankins , Ed Grochowski , Hong Wang , Murali Annavaram , David K. Poulsen , Sanjiv Shah , John Shen , Gautham Chinya
发明人： Ryan Rakvic , Richard A. Hankins , Ed Grochowski , Hong Wang , Murali Annavaram , David K. Poulsen , Sanjiv Shah , John Shen , Gautham Chinya
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.
摘要翻译： 确定在多处理器的第一处理单元上执行的第一线程的第一执行时间。 确定在多处理器的第二处理单元上执行的第二线程的第二执行时间，第一和第二线程并行执行。 功率被设置为第一和第二处理单元，以在第一和第二线程的将来执行中在大致相同的时刻实现第一和第二线程完成执行。 还描述和要求保护其他实施例。
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公开(公告)号：US07260705B2
公开(公告)日：2007-08-21
申请号：US10608316
申请日：2003-06-26
申请人： Hong Wang , John Shen , Perry Wang , Marsha Eng , Gerolf F. Hoflehner , Dan Lavery , Wei Li , Alejandro Ramirez , Ed Grochowski
发明人： Hong Wang , John Shen , Perry Wang , Marsha Eng , Gerolf F. Hoflehner , Dan Lavery , Wei Li , Alejandro Ramirez , Ed Grochowski
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F8/447 , G06F9/30181 , G06F9/30196 , G06F9/3808 , G06F9/3822 , G06F9/3836 , G06F9/3844
摘要： In one embodiment, the invention provides a method for examining information about branch instructions. A method, comprising: examining information about branch instructions that reach a write-back stage of processing within a processor, defining a plurality of streams based on the examining, wherein each stream comprises a sequence of basic blocks in which only a last block in the sequence ends in a branch instruction, the execution of which causes program flow to branch, the remaining basic blocks in the stream each ending in a branch instruction, the execution of which does not cause program flow to branch.
摘要翻译： 在一个实施例中，本发明提供了一种用于检查关于分支指令的信息的方法。 一种方法，包括：检查关于在处理器内达到处理的回写阶段的分支指令的信息，基于所述检查来定义多个流，其中每个流包括一系列基本块，其中仅一 序列在分支指令中结束，其执行导致程序流分支，流中的剩余基本块每个以分支指令结束，其执行不导致程序流分支。
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公开(公告)号：US5934163A
公开(公告)日：1999-08-10
申请号：US783151
申请日：1997-01-14
CPC分类号： B23B33/00 , Y10T279/17957 , Y10T82/25 , Y10T82/2561 , Y10T82/266 , Y10T83/384 , Y10T83/667
摘要： An improved carving blank and mandrel for mounting the blank in a carving machine enables accurate carving of prosthetic and orthotic positive shapes. The blanks are simple to mount and dismount and means are provided enabling a repeatable mounting position in one angular orientation only to be achieved. The blanks are firmly fixed in place on the mandrel during the carving operation, and they are simple and inexpensive to manufacture thus reducing manufacturing costs while achieving high shape accuracy.
摘要翻译： 用于将坯料安装在雕刻机中的改进的雕刻坯料和心轴能够准确地雕刻假体和矫正正形状。 坯件的安装和拆卸简单，并且提供了使得能够实现仅一个角度定向的可重复安装位置的装置。 在雕刻操作期间，坯料牢固地固定在心轴上，并且它们制造简单且便宜，从而降低制造成本，同时实现高的形状精度。
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公开(公告)号：US20180225117A1
公开(公告)日：2018-08-09
申请号：US15943611
申请日：2018-04-02
申请人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
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8.发明授权Load balancing for multi-threaded applications via asymmetric power throttling 有权通过不对称功率节流对多线程应用进行负载平衡公开(公告)号：US08839258B2
公开(公告)日：2014-09-16
申请号：US13354623
申请日：2012-01-20
申请人： Ryan Rakvic , Richard A. Hankins , Ed Grochowski , Hong Wang , Murali Annavaram , David K. Poulsen , Sanjiv Shah , John Shen , Gautham Chinya
发明人： Ryan Rakvic , Richard A. Hankins , Ed Grochowski , Hong Wang , Murali Annavaram , David K. Poulsen , Sanjiv Shah , John Shen , Gautham Chinya
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.
摘要翻译： 确定在多处理器的第一处理单元上执行的第一线程的第一执行时间。 确定在多处理器的第二处理单元上执行的第二线程的第二执行时间，第一和第二线程并行执行。 功率被设置为第一和第二处理单元，以在第一和第二线程的将来执行中在大致相同的时刻实现第一和第二线程完成执行。 还描述和要求保护其他实施例。
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9.发明授权Mechanism for instruction set based thread execution on a plurality of instruction sequencers 有权基于多个指令定序器的基于指令集的线程执行的机制公开(公告)号：US08719819B2
公开(公告)日：2014-05-06
申请号：US11173326
申请日：2005-06-30
申请人： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
发明人： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
IPC分类号： G06F9/46
CPC分类号： G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
摘要翻译： 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。
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10.发明申请LOAD BALANCING FOR MULTI-THREADED APPLICATIONS VIA ASYMMETRIC POWER THROTTLING 有权通过不对称功率曲线的多线程应用的负载平衡公开(公告)号：US20120131366A1
公开(公告)日：2012-05-24
申请号：US13354623
申请日：2012-01-20
申请人： Ryan Rakvic , Richard A. Hankins , Ed Grochowski , Hong Wang , Murali Annavaram , David K. Poulsen , Sanjiv Shah , John Shen , Gautham Chinya
发明人： Ryan Rakvic , Richard A. Hankins , Ed Grochowski , Hong Wang , Murali Annavaram , David K. Poulsen , Sanjiv Shah , John Shen , Gautham Chinya
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.
摘要翻译： 确定在多处理器的第一处理单元上执行的第一线程的第一执行时间。 确定在多处理器的第二处理单元上执行的第二线程的第二执行时间，第一和第二线程并行执行。 功率被设置为第一和第二处理单元，以在第一和第二线程的将来执行中在大致相同的时刻实现第一和第二线程完成执行。 还描述和要求保护其他实施例。
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