公开(公告)号：US4985640A

公开(公告)日：1991-01-15

申请号：US472598

申请日：1990-04-04

申请人： Edward Grochowski ,  Rajesh Gupta

发明人： Edward Grochowski ,  Rajesh Gupta

IPC分类号： H03K5/15 ,  H03K5/151

CPC分类号： H03K5/151 ,  H03K5/15006

摘要： A circuit for generating a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator including apparatus for generating first and second pair of signals at half the frequency of the input signal generated by a crystal oscillator, the signals of each pair being of opposite phase to one another; apparatus for comparing a first signal of the first pair signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus for comparing the second signal of the first pair of signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair of signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases; apparatus for producing a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator; and apparatus responsive to the apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases for equalizing the duty cycle of the pair of closk pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator.

摘要翻译： 一种用于产生相对相位的一对时钟脉冲的电路，每个时钟脉冲具有与由晶体振荡器产生的输入信号的频率相同的频率，该晶体振荡器包括用于产生第一和第二对信号的信号，所述第一和第二对信号的频率为由 晶体振荡器，每对信号彼此相反; 用于将第一对信号的第一信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 用于将第一对信号的第二信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 利用所述输出信号之一来延长所述第一对相对相位信号中的一个的占空比以及所述输出信号中的另一个的占空比，以缩短所述第一对相对相位信号中另一个的占空比; 用于产生具有与由晶体振荡器产生的输入信号的频率相同频率的相反相位的一对时钟脉冲的装置; 以及响应于所述装置的设备，利用所述输出信号之一来延长所述第一对相对相位信号之一的占空比，并且输出信号中的另一个信号的占空比，以缩短所述第一对信号中另一个的相反的占空比 用于均衡相位相对的一对闭合脉冲的占空比的相位，每个相位相位的频率与由晶体振荡器产生的输入信号的频率相同。

公开(公告)号：US20070164787A1

公开(公告)日：2007-07-19

申请号：US11234548

申请日：2005-09-23

申请人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

发明人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

摘要翻译： 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US06938126B2

公开(公告)日：2005-08-30

申请号：US10121524

申请日：2002-04-12

申请人： Alejandro Ramirez ,  Edward Grochowski ,  Hong Wang ,  John Shen

发明人： Alejandro Ramirez ,  Edward Grochowski ,  Hong Wang ,  John Shen

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F12/0882 ,  G06F12/0886 ,  Y02D10/13

摘要： A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.

摘要翻译： 将具有第一起始地址和与当前取出请求相关联的长度的当前提取请求与下一个提取请求的第二起始地址进行比较的方法，装置和系统确定已经加载在缓冲器中的内容是否将被用于 至少部分地基于比较来完成下一个提取请求，并且基于比较来禁止对指令高速缓存的访问。

公开(公告)号：US06904502B2

公开(公告)日：2005-06-07

申请号：US10743069

申请日：2003-12-23

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/16 ,  G11C7/24

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.

摘要翻译： 本发明涉及高可靠性高性能微处理器的设计，更具体地涉及在高速存储器中使用盲目无效电路的设计。 根据本发明的实施例，一种标签阵列存储电路，包括耦合在一起以形成n位存储单元的多个存储器位电路; 以及与n位存储器单元中的存储器位电路耦合的盲目无效电路，盲目无效电路清除存储器位电路中的一位，如果主清零位线被断言，并且接收到的位值为右， 相邻的存储器位电路为零。

公开(公告)号：US06813628B2

公开(公告)日：2004-11-02

申请号：US09746771

申请日：2000-12-22

申请人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

发明人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

IPC分类号： G06F704

CPC分类号： G06F7/5095 ,  G06F7/02 ,  G06F7/026 ,  G06F7/48 ,  G06F7/4824

摘要： A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.

摘要翻译： 公开了一种方法和装置，用于比较相等的数字。 减去以冗余形式表示的数字，包括从旁路电路接收的数字。更具体地，产生补码形式并将其提供给用冗余形式表示的至少一个数字的运算电路。 调整运算电路的输入以增加通过算术电路产生的结果，以产生作为减法运算的结果以冗余形式表示的有效结果。 使用非传播电路将减法操作的结果与冗余形式进行比较，而不需要进位传播，从而产生冗余形式的数量的等式比较。

公开(公告)号：US06775746B2

公开(公告)日：2004-08-10

申请号：US10435386

申请日：2003-05-12

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F1210

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

公开(公告)号：US20170199825A1

公开(公告)日：2017-07-13

申请号：US15384054

申请日：2016-12-19

申请人： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

发明人： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC分类号： G06F12/1009 ,  G06F12/14 ,  G06F12/0864 ,  G06F12/1027

CPC分类号： G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US20130219399A1

公开(公告)日：2013-08-22

申请号：US13843164

申请日：2013-03-15

申请人： Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

发明人： Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

IPC分类号： G06F9/48

CPC分类号： G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

摘要翻译： 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

公开(公告)号：US20110154000A1

公开(公告)日：2011-06-23

申请号：US12653800

申请日：2009-12-18

申请人： Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

发明人： Joshua B. Fryman ,  Andrew Thomas Forsyth ,  Edward Grochowski

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F9/3004 ,  G06F9/30087

摘要： A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.

摘要翻译： 公开了一种执行快速比较交换操作的技术。 更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。

公开(公告)号：US07395304B2

公开(公告)日：2008-07-01

申请号：US10890848

申请日：2004-07-13

申请人： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

发明人： Bharat Bhushan ,  Vinod Sharma ,  Edward Grochowski ,  John Crawford

IPC分类号： G06F7/04

CPC分类号： G06F7/5095 ,  G06F7/02 ,  G06F7/4824

摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction. Then the result is compared to a given value using a non-propagative comparator to determine equality or inequality of the result to the given value.

摘要翻译： 公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，还可以减去以冗余形式接收的数字，包括从旁路电路接收的数字。 然后使用非传播比较器电路将给定值与运算电路的结果进行比较，以确定结果是否等于给定值。 可以在整个电路中不传播进位信号来实现上述所有操作。 该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。 它还包括向算术电路提供调整输入以增加通过运算电路产生的结果。 如果算术运算是减法，则该调整使得运算电路作为减法运算的结果以冗余形式产生有效结果。 然后将结果与使用非传播比较器的给定值进行比较，以确定结果与给定值的相等或不等式。