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12 条记录 (耗时 0.017 秒)

    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5381372A

    公开(公告)日：1995-01-10

    申请号：US56919

    申请日：1993-05-05

    申请人： Eiji Kozuka ,  Naokazu Miyawaki

    发明人： Eiji Kozuka ,  Naokazu Miyawaki

    IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C29/26 ,  G11C29/48 ,  H01L21/66 ,  H01L27/10 ,  G11C29/00

    CPC分类号： G11C29/48 ,  G11C29/26

    摘要： A semiconductor memory device has a plurality of memory cell arrays; input and output sections each provided so as to correspond to each of the memory cell arrays; and an allocating section provided between the memory cell arrays and the input and output sections, for allocating one of the memory cell arrays to one of the input output sections in ordinary mode, and a plurality of the memory cell arrays to one of the input and output sections in test mode. In the operation test mode, since only a part of the input and output sections are used, it is possible to decrease the number of chips connected to the I/O pins (whose maximum number is limited) of the tester so as to be testable simultaneously, so that the number of chips whose operation tests can be implemented simultaneously can be increased, thus reducing the time required for the operation test of the memory device as a whole.

    摘要翻译： 半导体存储器件具有多个存储单元阵列; 每个所述输入和输出部分被提供以对应于每个所述存储单元阵列; 以及设置在所述存储单元阵列与所述输入和输出部分之间的分配部分，用于将所述存储单元阵列中的一个以普通模式分配到所述输入输出部分中的一个，以及将所述多个所述存储单元阵列分配给所述输入和 输出部分在测试模式。 在操作测试模式下，由于仅使用输入和输出部分的一部分，所以可以减少连接到测试仪的I / O引脚（其最大数量受限制）的芯片数量，以便可测试 同时，可以增加同时实现操作测试的芯片的数量，从而减少了整体上存储装置的操作测试所需的时间。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5337286A

    公开(公告)日：1994-08-09

    申请号：US993854

    申请日：1992-12-21

    申请人： Osamu Ohto ,  Tomoyuki Hamano ,  Eiji Kozuka ,  Naokazu Miyawaki

    发明人： Osamu Ohto ,  Tomoyuki Hamano ,  Eiji Kozuka ,  Naokazu Miyawaki

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C29/00 ,  G11C29/24 ,  G11C29/42 ,  H01L27/10 ,  G11C5/06

    CPC分类号： G11C7/1006 ,  G11C29/24 ,  G11C7/10

    摘要： A semiconductor memory device is adapted for storing, as a unit of memory information, multiple-bit data constituted by signal data comprised of bit data of 2.sup.n bits (n is a natural number) and remainder data comprised of bit data of C bits (C is a natural number, C

    摘要翻译： 一种半导体存储器件适用于存储作为存储器信息的单元，由由2n位（n是自然数）的位数据组成的信号数据构成的多位数据以及由C位（C 是自然数，C <2n）。 该半导体存储器件包括多个电路块，其包括例如由多个存储单元组成的两个存储单元组，以及行解码器和列解码器，适于允许存储单元组内的各个存储单元 有选择地活跃。 因此，行解码器和列解码器变得可操作，使得用作信号数据的位数据被分配给一个或多个电路块一位或多位，并且用作剩余数据的位数据被分配给任何电路 已经进行了位分配的块。

    Impedance control circuit for a semiconductor substrate
    4.
    发明授权
    Impedance control circuit for a semiconductor substrate 失效
    用于半导体衬底的阻抗控制电路

    公开(公告)号：US5270583A

    公开(公告)日：1993-12-14

    申请号：US687188

    申请日：1991-04-18

    申请人： Naokazu Miyawaki ,  Kiyoharu Murakami

    发明人： Naokazu Miyawaki ,  Kiyoharu Murakami

    IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/408 ,  H01L21/822 ,  H03K3/01

    CPC分类号： G05F3/205

    摘要： The semiconductor circuit device comprises a substrate bias generating circuit, a substrate voltage detecting circuit, and a substrate impedance adjusting circuit. When the detected substrate voltage decreases below a predetermined level, the substrate impedance adjusting circuit forms a through route between a substrate voltage terminal and any given terminal higher in potential than the substrate voltage terminal, to increase the substrate voltage at high speed, thus stabilizing threshold voltages or operation limit voltages of device elements which are subjected to the influence of the substrate voltage. Further, when the substrate voltage returns to the predetermined level, the substrate impedance adjusting circuit cuts off the formed through route for reduction of power consumption.

    摘要翻译： 半导体电路器件包括衬底偏置产生电路，衬底电压检测电路和衬底阻抗调节电路。 当检测到的衬底电压降低到预定水平以下时，衬底阻抗调整电路在衬底电压端子和电压高于衬底电压端子的任何给定端子之间形成通路，以高速增加衬底电压，从而稳定阈值 受到基板电压影响的器件元件的电压或工作极限电压。 此外，当基板电压恢复到预定电平时，基板阻抗调节电路切断形成的通路以降低功耗。

    Substrate bias voltage generator circuit
    5.
    发明授权
    Substrate bias voltage generator circuit 失效
    基板偏压发生电路

    公开(公告)号：US5243228A

    公开(公告)日：1993-09-07

    申请号：US865258

    申请日：1992-04-08

    申请人： Keiji Maruyama ,  Naokazu Miyawaki

    发明人： Keiji Maruyama ,  Naokazu Miyawaki

    IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/408 ,  H01L21/822

    CPC分类号： G05F3/205

    摘要： A substrate bias voltage generator circuit has a substrate bias voltage detector circuit, a substrate bias driver circuit, and a charge pump circuit. the substrate bias voltage detector circuit detects a substrate bias voltage applied to a semiconductor substrate and outputs a substrate bias voltage detection signal. The substrate bias detector circuit includes a P-channel transistor with a gate terminal and an N-channel transistor with a substrate terminal, both terminals being connected to the semiconductor substrate and the substrate bias voltage which is a back bias for the N-channel transistor. The substrate bias driver circuit is responsive to the substrate bias voltage detection signal outputted from the substrate bias voltage detector circuit, and outputs a drive signal when the absolute value of the substrate bias voltage is equal to or smaller than a predetermined value, and stops outputting the drive signal when the absolute value of the substrate bias voltage is larger than the predetermined value. The charge pump circuit is responsive to the drive signal from the substrate bias driver circuit, and generates the substrate bias voltage.

    摘要翻译： 衬底偏置电压发生器电路具有衬底偏置电压检测器电路，衬底偏置驱动器电路和电荷泵电路。 衬底偏置电压检测器电路检测施加到半导体衬底的衬底偏置电压并输出衬底偏置电压检测信号。 衬底偏置检测器电路包括具有栅极端子的P沟道晶体管和具有衬底端子的N沟道晶体管，两个端子连接到半导体衬底，并且衬底偏压作为N沟道晶体管的反偏压 。 衬底偏置驱动器电路响应于从衬底偏置电压检测器电路输出的衬底偏置电压检测信号，并且当衬底偏置电压的绝对值等于或小于预定值时输出驱动信号，并且停止输出 当衬底偏置电压的绝对值大于预定值时的驱动信号。 电荷泵电路响应于来自衬底偏置驱动器电路的驱动信号，并产生衬底偏置电压。

    Control circuit for controlling an operation mode in a pseudo-static ram
    7.
    发明授权
    Control circuit for controlling an operation mode in a pseudo-static ram 失效
    用于控制伪静态RAM中的操作模式的控制电路

    公开(公告)号：US5301164A

    公开(公告)日：1994-04-05

    申请号：US702375

    申请日：1991-05-20

    申请人： Naokazu Miyawaki

    发明人： Naokazu Miyawaki

    IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C11/403 ,  G11C11/4076 ,  G11C7/00

    CPC分类号： G11C11/40615 ,  G11C11/4076 ,  G11C7/22

    摘要： A control circuit for controlling an operation mode in a pseudo-static RAM. A chip enable control circuit generates a first group of control signals in synchronism with a change in level of a chip enable signal. A second control circuit receives a chip select signal and the first group of control signals, latches a chip select signal on the basis of a signal of the first group of control signals, and generates a second control signal in accordance with the latched signal. A third control circuit controls a write enable signal with an inverted replica of the second control signal and an inverted replica of a predetermined one of the first control signals in the first group of control signals.

    摘要翻译： 一种用于控制伪静态RAM中的操作模式的控制电路。 芯片使能控制电路与芯片使能信号的电平变化同步地产生第一组控制信号。 第二控制电路接收片选信号和第一组控制信号，基于第一组控制信号的信号锁存芯片选择信号，并根据锁存信号产生第二控制信号。 第三控制电路在第一组控制信号中以第二控制信号的反相副本和第一控制信号中的预定一个控制信号的反相副本来控制写使能信号。

    Apparatus for controlling circuit response during power-up
    8.
    发明授权
    Apparatus for controlling circuit response during power-up 有权
    用于控制上电期间电路响应的装置

    公开(公告)号：US5995436A

    公开(公告)日：1999-11-30

    申请号：US187153

    申请日：1998-11-06

    申请人： Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

    发明人： Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

    IPC分类号： G11C11/41 ,  G11C5/14 ,  G11C7/20 ,  G11C7/22 ,  G11C11/401

    CPC分类号： G11C7/22 ,  G11C5/143 ,  G11C7/20

    摘要： A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

    摘要翻译： 体现本发明的电路包括响应于第一控制信号的门控电路和具有活动状态和非活动状态的第二外部提供的控制信号。 第一控制信号由电源电路产生，电源电路响应于施加外部提供的工作电压以产生“内部”工作电压，并且当内部工作电压达到预定的工作电压时产生具有有效状态的第一控制信号 值。 门控电路具有用于产生第三控制信号的输出，该第三控制信号仅在第一控制信号已经处于其活动状态时才能使第二控制信号从其无效状态变为其活动状态。 门控电路可防止芯片在上电时以非预期模式运行。

    Chip enable input circuit in semiconductor memory device
    9.
    发明授权
    Chip enable input circuit in semiconductor memory device 失效
    半导体存储器件中的芯片使能输入电路

    公开(公告)号：US4970694A

    公开(公告)日：1990-11-13

    申请号：US351231

    申请日：1989-05-12

    申请人： Hiroaki Tanaka ,  Naokazu Miyawaki

    发明人： Hiroaki Tanaka ,  Naokazu Miyawaki

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C8/18

    CPC分类号： G11C8/18 ,  G11C8/12

    摘要： A first chip enable signal for determining the operation timing of a memory chip is supplied to a first chip enable input circuit. A second chip enable signal for selectively specifying the stand-by mode/operative mode of the memory chip and an output signal of the first chip enable input circuit are supplied to a second chip enable input circuit. The second chip enable signal is received and latched by means of the second chip enable input circuit when the first chip enable signal is set active. An internal chip enable signal is output from the second chip enable input circuit based on the latched output to set the internal circuit of the memory chip into the stand-by mode.

    Memory clock pulse generating circuit with reduced peak current requirements
    10.
    发明授权
    Memory clock pulse generating circuit with reduced peak current requirements 失效
    具有降低峰值电流要求的存储器时钟脉冲发生电路

    公开(公告)号：US4644184A

    公开(公告)日：1987-02-17

    申请号：US548730

    申请日：1983-11-04

    申请人： Naokazu Miyawaki ,  Mitsugi Ogura

    发明人： Naokazu Miyawaki ,  Mitsugi Ogura

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  H03K5/135 ,  G11C19/00 ,  H03K17/28 ,  H03K17/687

    CPC分类号： G11C11/406 ,  Y10S257/93

    摘要： A dynamic type semiconductor memory device having refreshing function includes a clock pulse generating circuit having a row clock pulse generating section which includes a plurality of cascade-connected delay circuits, a plurality of MOS transistors selectively connected between said delay circuits, and a gate control circuit for changing conduction resistances of the MOS transistors according to the level of a refreshing signal.

    摘要翻译： 具有刷新功能的动态型半导体存储器件包括具有行时钟脉冲发生部分的时钟脉冲发生电路，该行时钟脉冲产生部分包括多个级联连接的延迟电路，选择性地连接在所述延迟电路之间的多个MOS晶体管和门控制电路 用于根据刷新信号的电平来改变MOS晶体管的导通电阻。