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1.发明授权Process for the collective removal of resist material and side wall protective film 失效用于集体除去抗蚀剂材料和侧壁保护膜的方法公开(公告)号：US06436220B1
公开(公告)日：2002-08-20
申请号：US09367099
申请日：1999-08-10
IPC分类号： B32B3120
CPC分类号： H01L21/02071 , G03F7/34 , H01L21/027 , Y10T156/11
摘要： The present invention is intended to collectively remove unnecessary resist material and side wall protective film after dry etching by side wall protection process, making it possible to simplify the process for the preparation of semiconductors, etc. The process according to the present invention comprises removing unnecessary resist material (3) left behind after dry etching by side wall protection process with a resist pattern (3) present on a semiconductor substrate (2) as a mask and side wall protective film (4) deposited on the side wall (22) of pattern, said process comprising the steps of applying an pressure-sensitive adhesive sheet (1) to said substrate (2), heating the pressure-sensitive adhesive layer (1) under pressure so that the pressure-sensitive adhesive (11) comes in contact with up to the side wall (4) of pattern, and then collectively peeling said pressure-sensitive adhesive sheet (1), said resist material (3) and said side wall protective film (4) off said substrate.
摘要翻译： 本发明旨在通过侧壁保护工艺在干蚀刻之后集中地去除不需要的抗蚀剂材料和侧壁保护膜，从而可以简化制备半导体等的工艺。根据本发明的方法包括去除不必要的 在作为掩模的半导体基板（2）上存在的抗蚀剂图案（3）通过侧壁保护处理在干蚀刻后留下的抗蚀剂材料（3）和沉积在侧壁（22）上的侧壁保护膜（4） 所述方法包括以下步骤：将压敏粘合片（1）施加到所述基底（2）上，在压力下加压压敏粘合剂层（1），使得压敏粘合剂（11）接触 直到图案的侧壁（4），然后将所述压敏粘合片（1），所述抗蚀剂材料（3）和所述侧壁保护膜（4）从所述基体上共同剥离 te。
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公开(公告)号：US20070076203A1
公开(公告)日：2007-04-05
申请号：US11535300
申请日：2006-09-26
申请人： Takeo Ishibashi , Seiichiro Shirai
发明人： Takeo Ishibashi , Seiichiro Shirai
IPC分类号： G01J4/00
CPC分类号： G03F7/7085 , G01J1/0429 , G01J1/4257 , G03F7/70341 , G03F7/70566 , G03F9/7026 , G03F9/7065 , G03F9/7088
摘要： An exposure apparatus includes an illumination optical system having an exposure light source for emitting an exposure light, a projection optical system for guiding the exposure light to a substrate, a detection light source for emitting the detection light for detecting a focal point at a time of exposure, a polarizer capable of polarizing the detection light emitted from the detection light source into a specified polarized light, and a light detector for detecting the detection light polarized into the specified polarized light by the polarizer.
摘要翻译： 曝光装置包括具有用于发射曝光光的曝光光源的照明光学系统，用于将曝光光引导到基板的投影光学系统，用于发射用于检测焦点的检测光的检测光源 曝光，能够将从检测光源发射的检测光偏振到特定偏振光的偏振器，以及用于检测由偏振器偏振成特定偏振光的检测光的光检测器。
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公开(公告)号：US5736300A
公开(公告)日：1998-04-07
申请号：US694263
申请日：1996-08-08
CPC分类号： G03F1/26 , G03F1/29 , G03F1/30 , G03F7/70283 , G03F7/70433
摘要： One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.
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公开(公告)号：US5578422A
公开(公告)日：1996-11-26
申请号：US443431
申请日：1995-05-18
CPC分类号： G03F1/26 , G03F1/29 , G03F1/30 , G03F7/70283 , G03F7/70433
摘要： One object of the present invention is to provide the reduced projection exposure method which enables the exposure of various and fine patterns in manufacturing process of semiconductor devices or semiconductor integrated circuit devices. Structure of the present invention to attain the above object is to carry out the reduced projection exposure using a phase shift mask provided with a prescribed correction pattern on the end of the mask pattern domain of a constant mode or the boundary of the mask pattern domain of plural modes. According to this structure, as the end effects etc. are canceled by the correction pattern, the various and fine patterns can be exposed.
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公开(公告)号：US5405810A
公开(公告)日：1995-04-11
申请号：US869174
申请日：1992-04-16
申请人： Fumio Mizuno , Noboru Moriuchi , Seiichiro Shirai
发明人： Fumio Mizuno , Noboru Moriuchi , Seiichiro Shirai
IPC分类号： G03F9/00 , H01J37/304 , H01L21/027 , H01L21/30 , H01L21/68 , H01L23/544 , H01L21/312
CPC分类号： G03F9/70 , H01J37/3045 , H01L21/682 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： The present invention enables the accuracy of aligning a wafer and a reticle with each other in the exposure step in the manufacture of a semiconductor integrated circuit device to be improved. The portions of a metal film 5 and a resist film 6 which cover an alignment mark 4 on a wafer 1 are removed by a gas assisted etching treatment using a laser beam prior to the execution of an exposure treatment, so as to bare the alignment mark 4. The position detecting light is then applied from an alignment mark position detecting means in a reduction projection exposure unit 11 to the alignment mark 4, the position of the alignment mark 4 being detected on the basis of the light reflected on and scattered from the alignment mark 4.
摘要翻译： 本发明使半导体集成电路器件的制造中的曝光步骤中的晶片和掩模版之间的对准精度得以提高。 在执行曝光处理之前，通过使用激光束的气体辅助蚀刻处理去除覆盖晶片1上的对准标记4的金属膜5和抗蚀剂膜6的部分，以便露出对准标记 然后，将位置检测光从缩小投影曝光单元11中的对准标记位置检测装置施加到对准标记4，基于从其反射和散射的光检测对准标记4的位置 对准标记4。
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6.发明授权公开(公告)号：US07875409B2
公开(公告)日：2011-01-25
申请号：US11602505
申请日：2006-11-21
CPC分类号： G03F7/70475 , G03F1/00 , G03F7/70466 , G03F9/7076
摘要： A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.
摘要翻译： 提出了一种制造半导体器件的方法，该半导体器件通过在连接曝光中以良好的再现性和通过该方法制造的半导体器件正确地将相邻的小图案彼此正确地连接，从而对电路进行精细化。 根据这种制造半导体器件的方法，通过将形成在半导体衬底上的图案划分为多个图案并且以连接方式暴露多个分割图案，通过形成用于调整图案布置的标记来进行连接曝光 在暴露半导体元件的图案之前，在半导体基板上彼此连接，并且将半导体元件的图案与用于调整布置的标记连接地曝光。
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公开(公告)号：US5959011A
公开(公告)日：1999-09-28
申请号：US751254
申请日：1996-11-18
申请人： Fumio Mizuno , Noburu Moriuchi , Seiichiro Shirai , Yutaka Moroishi , Makoto Sunakawa , Michirou Kawanishi
发明人： Fumio Mizuno , Noburu Moriuchi , Seiichiro Shirai , Yutaka Moroishi , Makoto Sunakawa , Michirou Kawanishi
CPC分类号： B29C63/0013 , G03F7/343 , G03F7/42 , Y10S156/922 , Y10T156/11 , Y10T156/1189
摘要： A method for removing a resist pattern formed on a semiconductor wafer, and a curable pressure-sensitive adhesive, adhesive sheets and an apparatus used for the method. The resist-removing method comprising adhering an adhesive tape on an upper surface of a resist pattern formed on an article and peeling off the resist pattern together with the adhesive tape; the curable pressure-sensitive adhesive constituting the adhesive tape, comprising a pressure-sensitive adhesive polymer containing a non-volatile compound having at least one unsaturated double bond in the molecule and having a good affinity with a resist material to be removed; the adhesive sheet comprising a film substrate having formed thereon the curable pressure-sensitive adhesive; and the resist-removing apparatus comprising a means for press-adhering the adhesive tape, a tape-peeling means, and a substrate-washing means.
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公开(公告)号：US4835089A
公开(公告)日：1989-05-30
申请号：US60323
申请日：1987-06-10
申请人： Takao Iwayanagi , Norio Hasegawa , Toshihiko Tanaka , Hiroshi Shiraishi , Takumi Ueno , Michiaki Hashimoto , Seiichiro Shirai , Kazuya Kadota
发明人： Takao Iwayanagi , Norio Hasegawa , Toshihiko Tanaka , Hiroshi Shiraishi , Takumi Ueno , Michiaki Hashimoto , Seiichiro Shirai , Kazuya Kadota
IPC分类号： G03F7/095
CPC分类号： G03F7/095
摘要： A thick polymer film containing an aromatic bisazide and/or an aromatic sulfonyl azide compound is formed on a substrate having topography level on its surface to flatten said surface and then heated or the whole surface thereof is exposed to a light. A mask pattern having a dry etching resistance higher than that of the polymer is formed on the polymer film, exposed parts of the polymer film are removed by the dry etching and the exposed parts of the film to be processed are removed to form a pattern.
摘要翻译： 在其表面上具有表层水平的基底上形成含有芳族双叠氮化物和/或芳族磺酰基叠氮化合物的厚聚合物膜，以使所述表面变平，然后加热或将其整个表面曝光。 在聚合物膜上形成具有高于聚合物的耐干蚀刻性的掩模图案，通过干蚀刻除去聚合物膜的暴露部分，并除去待处理的膜的暴露部分以形成图案。
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9.发明授权Manufacturing method of semiconductor device, exposure method, and exposure apparatus 有权半导体器件的制造方法，曝光方法和曝光装置公开(公告)号：US08557611B2
公开(公告)日：2013-10-15
申请号：US13305858
申请日：2011-11-29
申请人： Seiichiro Shirai
发明人： Seiichiro Shirai
CPC分类号： G03F7/7085 , G03F7/70033 , G03F7/70141
摘要： An exposure apparatus includes a light emission part 10 generating EUV light by plasma excitation of a predetermined atom, a condenser part 20 condensing the EUV light emitted from the light emission part, an exposure part 30 irradiating a substrate via a mask with the EUV light condensed by the condenser part, a first plasma position monitor 11a detecting the position of an emission point of the EUV light within the light emission part, and a light emission part drive unit 13 adjusting the position of the light emission part. The exposure apparatus determines a first shift amount between the emission point detected by the plasma position monitor and a reference light emission position, and drives the light emission part drive unit according to the first shift amount.
摘要翻译： 曝光装置包括通过等离子体激发预定原子产生EUV光的发光部分10，聚光从发光部分发射的EUV光的聚光部20，通过掩模用EUV光聚光照射基板的曝光部30 通过冷凝器部分，检测发光部分内的EUV光的发射点的位置的第一等离子体位置监视器11a和调整发光部的位置的发光部驱动部13。 曝光装置确定由等离子体位置监视器检测的发射点与参考发光位置之间的第一偏移量，并根据第一移位量驱动发光部分驱动单元。
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10.发明申请公开(公告)号：US20070134564A1
公开(公告)日：2007-06-14
申请号：US11602505
申请日：2006-11-21
CPC分类号： G03F7/70475 , G03F1/00 , G03F7/70466 , G03F9/7076
摘要： A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.
摘要翻译： 提出了一种制造半导体器件的方法，该半导体器件通过在连接曝光中以良好的再现性和通过该方法制造的半导体器件正确地将相邻的小图案彼此正确地连接，从而对电路进行精细化。 根据这种制造半导体器件的方法，通过将形成在半导体衬底上的图案划分为多个图案并且以连接方式暴露多个分割图案，通过形成用于调整图案布置的标记来进行连接曝光 在暴露半导体元件的图案之前，在半导体基板上彼此连接，并且将半导体元件的图案与用于调整布置的标记连接地曝光。
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