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公开(公告)号：US08654563B2
公开(公告)日：2014-02-18
申请号：US13588644
申请日：2012-08-17
CPC分类号： G06F12/0238 , G06F3/0607 , G06F3/0664 , G06F3/0679 , G06F13/1694 , G06F2212/7201 , G11C11/005 , G11C11/5621 , G11C13/0004 , G11C16/0416 , G11C2211/5641 , Y02D10/13 , Y02D10/14
摘要： Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括包括用于控制非易失性存储器阵列的存储器控制器的装置和方法。 存储器控制器包括耦合到非易失性存储器阵列的存储器阵列接口，以在非易失性存储器阵列上执行读取和写入。 覆盖模块被配置为在接收到所需位值和逻辑地址之后，将所需位值写入非易失性存储器阵列内的特定存储器单元，而不管存储器单元的原始值。 描述附加的装置和方法。
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公开(公告)号：US20120317347A1
公开(公告)日：2012-12-13
申请号：US13588644
申请日：2012-08-17
IPC分类号： G06F12/02
CPC分类号： G06F12/0238 , G06F3/0607 , G06F3/0664 , G06F3/0679 , G06F13/1694 , G06F2212/7201 , G11C11/005 , G11C11/5621 , G11C13/0004 , G11C16/0416 , G11C2211/5641 , Y02D10/13 , Y02D10/14
摘要： Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括包括用于控制非易失性存储器阵列的存储器控制器的装置和方法。 存储器控制器包括耦合到非易失性存储器阵列以在非易失性存储器阵列上执行读取和写入的存储器阵列接口。 覆盖模块被配置为在接收到所需位值和逻辑地址之后，将所需位值写入非易失性存储器阵列内的特定存储器单元，而不管存储器单元的原始值。 描述附加的装置和方法。
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公开(公告)号：US08250282B2
公开(公告)日：2012-08-21
申请号：US12466366
申请日：2009-05-14
IPC分类号： G06F13/00
CPC分类号： G06F12/0238 , G06F3/0607 , G06F3/0664 , G06F3/0679 , G06F13/1694 , G06F2212/7201 , G11C11/005 , G11C11/5621 , G11C13/0004 , G11C16/0416 , G11C2211/5641 , Y02D10/13 , Y02D10/14
摘要： A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array.
摘要翻译： 描述了可以在存储总线接口上使用的用于相变存储器（PCM）的存储器控制器。 在一个示例中，存储器控制器包括耦合到外部总线的外部总线接口以与外部设备通信读取和写入指令，耦合到存储器阵列以在存储器阵列上执行读取和写入的存储器阵列接口以及覆盖 模块将期望的值写入存储器阵列的期望地址。
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公开(公告)号：US08706957B2
公开(公告)日：2014-04-22
申请号：US13620980
申请日：2012-09-15
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。
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公开(公告)号：US20130019058A1
公开(公告)日：2013-01-17
申请号：US13620980
申请日：2012-09-15
IPC分类号： G06F12/02
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。
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公开(公告)号：US08307151B1
公开(公告)日：2012-11-06
申请号：US12628152
申请日：2009-11-30
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An e-MMC memory having a controller for a NAND Flash and another controller for a Phase-Change Memory (PCM) in a memory managed system. The different memory technologies of the NAND Flash and PCM may be partitioned to segment available memory space to store different types of data or code while accounting for an attribute property stored in a register.
摘要翻译： 具有用于NAND闪存的控制器和用于存储器管理系统中的相变存储器（PCM）的另一个控制器的e-MMC存储器。 NAND Flash和PCM的不同存储器技术可以被划分成段可用存储器空间以存储不同类型的数据或代码，同时考虑存储在寄存器中的属性属性。
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7.发明授权Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface 有权与从第一接口到第二接口的操作过渡相关联的设备，电子设备和方法公开(公告)号：US08806164B2
公开(公告)日：2014-08-12
申请号：US13041288
申请日：2011-03-04
IPC分类号： G06F12/00
CPC分类号： G06F12/1466 , G06F3/0622 , G06F3/0637 , G06F3/0673 , G06F3/0679 , G06F12/00 , G06F12/14 , G06F13/1668 , G06F13/4036 , G06F13/4221 , G06F2212/1052
摘要： Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.
摘要翻译： 本文公开的主题涉及包括存储器和控制器的控制器，诸如控制器，其与共享至少一个存储器块的两个或多个接口之间的操作转换相关联地确定块锁定状态。 该装置可以支持单通道或多通道存储器访问，写保护状态逻辑或各种接口优先级方案。
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公开(公告)号：US08599638B2
公开(公告)日：2013-12-03
申请号：US13596822
申请日：2012-08-28
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C13/0004 , G11C16/04
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.
摘要翻译： 本文公开的主题涉及存储器件，更具体地涉及多通道存储器件以及选择其一个或多个通道的方法。
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公开(公告)号：US07903478B1
公开(公告)日：2011-03-08
申请号：US12355466
申请日：2009-01-16
IPC分类号： G11C7/00
摘要： A sense amplifier may be used to measure voltages and/or currents that represent logic levels stored in memory cells of memory devices. Accuracy and stability of such measurements may be improved by selective switching to isolate sense amplifiers from other portions of a circuit.
摘要翻译： 读出放大器可用于测量表示存储在存储器件的存储器单元中的逻辑电平的电压和/或电流。 这种测量的精度和稳定性可以通过选择性地切换以将读出放大器与电路的其它部分隔离来提高。
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公开(公告)号：US07782665B2
公开(公告)日：2010-08-24
申请号：US12039268
申请日：2008-02-28
IPC分类号： G11C16/04
CPC分类号： G11C16/3436
摘要： A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are read by reading respective ternary strings written in respective pairs of three-level cells and decoding each read ternary string in a corresponding string of three bits according to the coding scheme. A pair of adjacent bits, belonging to at least one of a same initial string and two initial adjacent strings, are programmed by identifying pairs of three-level cells to be programmed that encode the strings of three bits and programming each pair of three-level cells.
摘要翻译： 一种管理具有奇异寻址的三电平单元的多电平存储器件的方法包括通过根据编码方案将它们编码在相应的三进制字符串中来存储三位字符串，并将三个字符串中的每一个写入相应的一对三电平 细胞。 通过读取写在相应的三电平单元对中的各个三进制字符串来读取三位字符串，并根据编码方案对相应的三位串中的每个读取三进制串进行解码。 属于相同初始串和两个初始相邻串中的至少一个的一对相邻位通过识别对要编程的三电平单元的对来编程，所述三电平单元对三位串进行编程，并对每一对三电平进行编程 细胞。
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