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公开(公告)号：US08654563B2
公开(公告)日：2014-02-18
申请号：US13588644
申请日：2012-08-17
CPC分类号： G06F12/0238 , G06F3/0607 , G06F3/0664 , G06F3/0679 , G06F13/1694 , G06F2212/7201 , G11C11/005 , G11C11/5621 , G11C13/0004 , G11C16/0416 , G11C2211/5641 , Y02D10/13 , Y02D10/14
摘要： Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括包括用于控制非易失性存储器阵列的存储器控制器的装置和方法。 存储器控制器包括耦合到非易失性存储器阵列的存储器阵列接口，以在非易失性存储器阵列上执行读取和写入。 覆盖模块被配置为在接收到所需位值和逻辑地址之后，将所需位值写入非易失性存储器阵列内的特定存储器单元，而不管存储器单元的原始值。 描述附加的装置和方法。
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公开(公告)号：US20120317347A1
公开(公告)日：2012-12-13
申请号：US13588644
申请日：2012-08-17
IPC分类号： G06F12/02
CPC分类号： G06F12/0238 , G06F3/0607 , G06F3/0664 , G06F3/0679 , G06F13/1694 , G06F2212/7201 , G11C11/005 , G11C11/5621 , G11C13/0004 , G11C16/0416 , G11C2211/5641 , Y02D10/13 , Y02D10/14
摘要： Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括包括用于控制非易失性存储器阵列的存储器控制器的装置和方法。 存储器控制器包括耦合到非易失性存储器阵列以在非易失性存储器阵列上执行读取和写入的存储器阵列接口。 覆盖模块被配置为在接收到所需位值和逻辑地址之后，将所需位值写入非易失性存储器阵列内的特定存储器单元，而不管存储器单元的原始值。 描述附加的装置和方法。
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公开(公告)号：US08250282B2
公开(公告)日：2012-08-21
申请号：US12466366
申请日：2009-05-14
IPC分类号： G06F13/00
CPC分类号： G06F12/0238 , G06F3/0607 , G06F3/0664 , G06F3/0679 , G06F13/1694 , G06F2212/7201 , G11C11/005 , G11C11/5621 , G11C13/0004 , G11C16/0416 , G11C2211/5641 , Y02D10/13 , Y02D10/14
摘要： A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array.
摘要翻译： 描述了可以在存储总线接口上使用的用于相变存储器（PCM）的存储器控制器。 在一个示例中，存储器控制器包括耦合到外部总线的外部总线接口以与外部设备通信读取和写入指令，耦合到存储器阵列以在存储器阵列上执行读取和写入的存储器阵列接口以及覆盖 模块将期望的值写入存储器阵列的期望地址。
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公开(公告)号：US20110307762A1
公开(公告)日：2011-12-15
申请号：US13122909
申请日：2008-10-09
申请人： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
发明人： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC分类号： G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
摘要： A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
摘要翻译： 单个虚拟化ECC NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。
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公开(公告)号：US08458562B1
公开(公告)日：2013-06-04
申请号：US12346015
申请日：2008-12-30
申请人： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
发明人： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
CPC分类号： G11C29/42 , G06F11/1048 , G11C2029/0411
摘要： Embodiments for providing improved reliability or extended life for a non-volatile memory component may comprise a secondary non-volatile memory component to store error correction information, for example.
摘要翻译： 用于为非易失性存储器组件提供改进的可靠性或延长使用寿命的实施例可以包括例如存储纠错信息的次级非易失性存储器组件。
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6.发明授权Controller to execute error correcting code algorithms and manage NAND memories 有权控制器执行纠错码算法和管理NAND存储器公开(公告)号：US08806293B2
公开(公告)日：2014-08-12
申请号：US13122909
申请日：2008-10-09
申请人： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
发明人： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC分类号： G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
摘要： A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
摘要翻译： 单个虚拟化ECC NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。
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公开(公告)号：US08706957B2
公开(公告)日：2014-04-22
申请号：US13620980
申请日：2012-09-15
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。
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公开(公告)号：US20130019058A1
公开(公告)日：2013-01-17
申请号：US13620980
申请日：2012-09-15
IPC分类号： G06F12/02
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
摘要翻译： 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。
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公开(公告)号：US08307151B1
公开(公告)日：2012-11-06
申请号：US12628152
申请日：2009-11-30
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An e-MMC memory having a controller for a NAND Flash and another controller for a Phase-Change Memory (PCM) in a memory managed system. The different memory technologies of the NAND Flash and PCM may be partitioned to segment available memory space to store different types of data or code while accounting for an attribute property stored in a register.
摘要翻译： 具有用于NAND闪存的控制器和用于存储器管理系统中的相变存储器（PCM）的另一个控制器的e-MMC存储器。 NAND Flash和PCM的不同存储器技术可以被划分成段可用存储器空间以存储不同类型的数据或代码，同时考虑存储在寄存器中的属性属性。
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公开(公告)号：US20200004679A1
公开(公告)日：2020-01-02
申请号：US16023485
申请日：2018-06-29
IPC分类号： G06F12/0802 , G06F12/1009 , G06F12/02 , H04L9/08 , H04L9/32
摘要： Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.
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