摘要:
A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.
摘要:
A CMOS semiconductor device having shallow source/drain junctions is formed by ion implanting antimony to form lightly doped source/drain regions of an N-channel transistor, thereby reducing channeling for a shallower projected junction depth as compared to conventional N-type impurity implantations. Upon growing a thermal oxide screen layer to protect the substrate from subsequent ion implantations, the implanted antimony experiences oxidation-retarded diffusion, further reducing the projected junction depth. After ion implanting N-type impurities to form moderately or heavily doped source/drain regions and activation annealing, the resulting semiconductor device exhibits the desirably shallow LDD junctions.
摘要:
A semiconductor device with shallow junctions is obtained by forming shallow source/drain extensions followed by forming a film over the gate electrode and the semiconductor substrate. The film is formed having a targeted thicknesses to facilitate gate electrode doping and source/drain formation. Ion implantation is then conducted to fully dope the gate electrode and form moderately or heavily doped source/drain implants, thereby reducing gate depletion.
摘要:
A process in accordance with the invention enables the manufacturability of raised source-drain MOSFETs. In accordance with the invention, a raised source-drain material, having a window therein, is formed over the substrate. A gate oxide and window sidewall oxides are subsequently formed. Dopants are diffused into the substrate. A gate is formed within the window.
摘要:
A process in accordance with the invention minimizes the number of heat steps to which an source-drain extension region is exposed, thus minimizing source-drain extension region diffusion and allowing more precise control of source-drain extension region thickness over conventional processes. In accordance with the invention, spacers are formed abutting the gate and then heavily doped source and drain regions are formed. The gate and source and drain regions are silicided. The spacers are subsequently removed and source-drain extension regions are then formed. In one embodiment of the invention, a laser doping process is used to form the source-drain extension regions.
摘要:
A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要:
A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region.
摘要:
An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
摘要:
A silicon on insulator (SOI) wafer is formed with an unoxidized perforation in the insulating silicon dioxide buried oxide layer. A field effect transistor (FET) structure on the SOI wafer is located above the unoxidized perforation such that the unoxidized perforation provides for electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the FET includes masking a silicon wafer prior to an oxygen implantation process to form the unoxidized perforated buried oxide layer in the wafer.
摘要:
A method of making a lightly doped drain transistor includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and forming a drain (70) in a drain region (58) and a source (72) in a source region (60) of the substrate (56). The method further includes generating interstitials (62) near a lateral edge of at least one of the drain (70) and the source (72) and thermally treating the substrate (56). The thermal treatment cause the interstitials (62) to enhance a lateral diffusion (84) of the drain (70) under the gate oxide (54) without substantially impacting a vertical diffusion (82) of the drain (70) or the source (72). The enhanced lateral diffusion (84) results in the formation of at least one of a lightly doped drain extension region (75) and a lightly doped source extension region (76) without an increase in a junction depth of the drain (70) or the source (72). The step of generating interstitials (62) may include the step of implanting at least one of the drain region (58) and the source region (60) of the substrate (56) with a large tilt angle implant which creates the interstitials (62) at a location near the gate oxide (54).