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1.发明授权公开(公告)号：US08508266B2
公开(公告)日：2013-08-13
申请号：US13173694
申请日：2011-06-30
申请人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
发明人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
IPC分类号： H03L7/06
摘要： Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.
摘要翻译： 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。
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公开(公告)号：US20130002317A1
公开(公告)日：2013-01-03
申请号：US13173694
申请日：2011-06-30
申请人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
发明人： Emmanouil Frantzeskakis , Georgios Sfikas , Stephen Wu , Radha Srinivasan , Henrik Tholstrup Jensen , Brima Ibrahim
IPC分类号： H03L7/08
摘要： Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.
摘要翻译： 具有数字锁相环（DPLL）电路的器件的设计包括多个数字反馈回路，以通过数字控制振荡器（DCO）产生高频时钟信号。 在这种DPLL电路中提供时间数字转换器（TDC）模块，以从第一数字反馈回路接收输入参考时钟信号和第一反馈时钟信号，并产生指示第一相位误差的数字TDC输出 通过输入参考时钟信号和第一反馈时钟信号之间的时间差。 提供第二数字反馈环路以产生指示由期望时钟信号和由DCO产生的生成的时钟信号之间的频率差引起的第二相位误差的第二数字反馈信号。 第一和第二数字反馈回路耦合到DCO以产生高频时钟信号。
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公开(公告)号：US08471611B2
公开(公告)日：2013-06-25
申请号：US13466760
申请日：2012-05-08
IPC分类号： H03L7/06
CPC分类号： H04L7/0337 , H03L7/091 , H03L7/1976
摘要： The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone.
摘要翻译： 本公开涉及一种使用爆炸相位检测器（BBPD）代替常规使用的基于时间 - 数字转换器（TDC）的相位检测器的分数N数字锁相环（DPLL）。 与基于TDC的相位检测器相比，BBPD具有相同或相似的功率和/或面积消耗量的常规优异分辨率。 因此，由于基于TDC的相位检测器的分辨率有限，所以用BBPD代替基于TDC的相位检测器可以减少甚至消除由DPLL产生的输出信号中添加的杂散的常见问题。 这可以使得DPLL被用于最苛刻的应用中，诸如产生本地振荡器信号用于下变频和解调诸如蜂窝电话之类的通信设备接收的弱信号。
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4.发明授权公开(公告)号：US07869541B2
公开(公告)日：2011-01-11
申请号：US11561093
申请日：2006-11-17
IPC分类号： H04L25/03
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991 , H03C5/00
摘要： Aspects of a method and system for direct and polar modulation using a two input PLL are presented. Aspects of the system may include generating digital signals Wn and Vn from an input data signal Un and a feedback signal Yn. The generated digital signals Wn and Vn combined may carry the information content of Un while they compensate the non-idealities of the two-input analog phase locked loop (PLL). The digital signal Wn, which may be scaled appropriately in frequency, and the digital signal Vn may be provided as inputs to the PLL. The feedback signal Yn may be a digital signal that may correspond to the analog feedback signal Pt that may be generated by the PLL. Accordingly, the PLL may be adaptively controlled via the digital signals Wn and Vn for properly transmitting the input data signal Un.
摘要翻译： 提出了使用两个输入PLL进行直接和极坐标调制的方法和系统的方面。 该系统的方面可以包括从输入数据信号Un和反馈信号Yn产生数字信号Wn和Vn。 所生成的数字信号Wn和Vn组合可以携带Un的信息内容，同时它们补偿双输入模拟锁相环（PLL）的非理想性。 可以在频率上适当缩放的数字信号Wn和数字信号Vn可以被提供给PLL的输入。 反馈信号Yn可以是可以对应于可由PLL产生的模拟反馈信号Pt的数字信号。 因此，可以经由数字信号Wn和Vn自适应地控制PLL，以适当地发送输入数据信号Un。
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5.发明授权Digital phase-locked loop with wide capture range, low phase noise, and reduced spurs 失效数字锁相环具有宽捕捉范围，低相位噪声和减少杂散公开(公告)号：US08686771B2
公开(公告)日：2014-04-01
申请号：US13485413
申请日：2012-05-31
申请人： Emmanouil Frantzeskakis , Ioannis L. Syllaios , Georgios Sfikas , Henrik Jensen , Stephen Wu , Padmanava Sen
发明人： Emmanouil Frantzeskakis , Ioannis L. Syllaios , Georgios Sfikas , Henrik Jensen , Stephen Wu , Padmanava Sen
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/1976 , H03L2207/50
摘要： The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.
摘要翻译： 本公开涉及用于建立和维持所生成的输出信号和参考输入信号之间的相位关系的数字锁相环（DPLL）和混合锁相环（HPLL）。 DPLL使用基于计数器的循环来初始将DPLL锁定。 此后，DPLL禁用基于计数器的循环并切换到具有多模式分频器（MMD）的回路。 DPLL可以实现消除技术，以减少由MMD引入的相位噪声。 HPLL还包括一个带有MMD的循环。 HPLL可以实现类似的消除技术，以减少由MMD引入的相位噪声。
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6.发明申请公开(公告)号：US20080116986A1
公开(公告)日：2008-05-22
申请号：US11561093
申请日：2006-11-17
IPC分类号： H03C3/02
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991 , H03C5/00
摘要： Aspects of a method and system for direct and polar modulation using a two input PLL are presented. Aspects of the system may include generating digital signals Wn and Vn from an input data signal Un and a feedback signal Yn. The generated digital signals Wn and Vn combined may carry the information content of Un while they compensate the non-idealities of the two-input analog phase locked loop (PLL). The digital signal Wn, which may be scaled appropriately in frequency, and the digital signal Vn may be provided as inputs to the PLL. The feedback signal Yn may be a digital signal that may correspond to the analog feedback signal Pt that may be generated by the PLL. Accordingly, the PLL may be adaptively controlled via the digital signals Wn and Vn for properly transmitting the input data signal Un.
摘要翻译： 提出了使用两个输入PLL进行直接和极坐标调制的方法和系统的方面。 系统的方面可以包括从输入数据信号U N n N和/或从反馈信号Y N n N生成数字信号W n和V N n， n 。 组合的所生成的数字信号W N n和V N n N可以承载U N的信息内容，同时它们补偿二进制的非理想性， 输入模拟锁相环（PLL）。 可以适当地在频率上缩放的数字信号W N n N和数字信号V N n N可以被提供给PLL的输入。 反馈信号Y N可以是可以对应于可由PLL产生的模拟反馈信号P SUB的数字信号。 因此，可以经由数字信号W N和V N n N适配地控制PLL，以便适当地传输输入数据信号U N n。
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7.发明申请公开(公告)号：US20080095269A1
公开(公告)日：2008-04-24
申请号：US11552181
申请日：2006-10-24
IPC分类号： H04L27/12
CPC分类号： H03C5/00
摘要： Aspects of a method and system for digital tracking in direct and polar modulation are presented. Aspects of the system may include at least one circuit within a phase locked loop (PLL) circuit that enables adaptive and digital control of an analog fractional N (Frac N) PLL during direct modulation of a signal or polar modulation of the signal.
摘要翻译： 介绍了直接和极坐标调制中数字跟踪方法和系统的方面。 该系统的方面可以包括锁相环（PLL）电路中的至少一个电路，其能够在信号的直接调制或信号的极性调制期间对模拟分数N（Frac N）PLL进行自适应和数字控制。
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公开(公告)号：US20130113573A1
公开(公告)日：2013-05-09
申请号：US13436564
申请日：2012-03-30
CPC分类号： H03L7/099 , H03K3/0315
摘要： The present disclosure is directed to a method and apparatus for providing an output oscillating signal at a desired frequency. In at least one example, the apparatus includes a weak inversion structure configured to set a small reference current. A current mirror configured to provide a replica current based on the small reference current and a tuning word. A ring oscillator is configured to be powered by a supply at a voltage determined based on the replica current. The tuning word is adjustable to change the voltage such that the ring oscillator provides the output oscillating signal at the desired frequency.
摘要翻译： 本公开涉及一种用于以期望的频率提供输出振荡信号的方法和装置。 在至少一个示例中，该装置包括被配置为设置小参考电流的弱反转结构。 配置为基于小参考电流提供复制电流的电流镜和调谐字。 环形振荡器被配置为由基于复制电流确定的电压的电源供电。 调谐字可调，以改变电压，使得环形振荡器以期望的频率提供输出振荡信号。
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