公开(公告)号：US07787463B2

公开(公告)日：2010-08-31

申请号：US11407279

申请日：2006-04-20

申请人： Eric A. Baden

发明人： Eric A. Baden

IPC分类号： H04L12/28

CPC分类号： H04L49/90 ,  H04L45/7453 ,  H04L47/50 ,  H04L47/527 ,  H04L49/351 ,  H04L49/355 ,  H04L49/602 ,  H04L49/901 ,  H04L49/9078

摘要： An example network device includes a processor that is configured to apply specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The example network device is configured to enable selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The specific fields include a plurality of fields some of which include multiple field values and definitions. An input bit map field of one of the plurality of fields is used to provide an additional global mask that is ANDed to associated masks in selected entries in the memory device thereby enabling the memory device to output an OR of the data in the selected entries and thereby allowing multiple ports to share a rule within a memory device entry.

摘要翻译： 示例性网络设备包括被配置为将特定字段从分组应用到相关联的存储器设备的处理器，以及用于将存储器设备的输入与存储器设备中的条目进行比较的比较装置。 示例网络设备被配置为使得能够选择由存储器设备选择与从输入到存储器设备的位精确匹配的位。 特定字段包括多个字段，其中一些字段包括多个字段值和定义。 使用多个字段之一的输入位图字段来提供附加全局掩码，该附加全局掩码与存储器件中所选条目中的关联掩码进行“与”运算，从而使存储器件能够输出所选条目中的数据的或， 从而允许多个端口在存储器设备条目内共享规则。

公开(公告)号：US07583588B2

公开(公告)日：2009-09-01

申请号：US11099530

申请日：2005-04-06

申请人： Michael J. Bowes ,  Eric A. Baden ,  John Jeffrey Dull ,  Curt McDowell

发明人： Michael J. Bowes ,  Eric A. Baden ,  John Jeffrey Dull ,  Curt McDowell

IPC分类号： H04L12/26 ,  G06F15/177

CPC分类号： H04L49/3072 ,  H04L49/201 ,  H04L49/3009 ,  H04L49/351 ,  H04L49/508

摘要： A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

摘要翻译： 用于处理数据包的网络设备。 网络设备包括用于执行用于层2切换的查找并执行维护层2表的操作的入口模块。 当入口模块更新第2层表时，入口模块将修改缓冲区中的第2层表上执行的操作记录下来。 当修改第2层表时，按照修改第2层表的顺序将条目添加到修改缓冲区。 因此，通过执行修改缓冲器中的操作，网络设备能够重构第2层。

公开(公告)号：US08000324B2

公开(公告)日：2011-08-16

申请号：US11100537

申请日：2005-04-07

申请人： Anupam Anand ,  John Jeffrey Dull ,  Eric A. Baden ,  Michael J. Bowes

发明人： Anupam Anand ,  John Jeffrey Dull ,  Eric A. Baden ,  Michael J. Bowes

IPC分类号： H04L12/56

CPC分类号： H04L49/90

摘要： A network device for processing packets. The network device includes an ingress module for performing switching functions on an incoming packet. The network device also includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to an appropriate destination port. Each of the ingress module, memory management unit and egress module includes multiple cycles for processing instructions and each of the ingress module, memory management unit and egress module processes one packet every clock cycle.

摘要翻译： 用于处理数据包的网络设备。 网络设备包括用于对输入分组执行切换功能的入口模块。 网络设备还包括用于存储分组并对每个分组执行资源检查的存储器管理单元和用于执行分组修改并将分组发送到适当的目的地端口的出口模块。 入口模块，存储器管理单元和出口模块中的每一个包括用于处理指令的多个周期，并且入口模块，存储器管理单元和出口模块中的每一个每个时钟周期处理一个分组。

公开(公告)号：US07787471B2

公开(公告)日：2010-08-31

申请号：US10985033

申请日：2004-11-10

申请人： Eric A. Baden ,  Mohan Kalkunte ,  John J. Dull ,  Venkateshwar Buduma

发明人： Eric A. Baden ,  Mohan Kalkunte ,  John J. Dull ,  Venkateshwar Buduma

IPC分类号： H04L12/54

CPC分类号： H04L47/10 ,  H04L45/7453 ,  H04L47/20 ,  H04L47/2408 ,  H04L47/2441 ,  H04L47/2458 ,  H04L47/32 ,  H04L69/22

摘要： A method of handling a datagram in a network device is disclosed. The steps include receiving a datagram, with the datagram having multiple field values, at a port of a network device, parsing the received datagram to obtain the field values, applying the parsed field values to a Ternary Content Addressable Memory (TCAM), determining matches between the parsed field values and predetermined criteria in the TCAM, indexing into a policy table based on the determined matches to obtain an action entry and taking an action based on the obtained action entry.

摘要翻译： 公开了一种在网络设备中处理数据报的方法。 这些步骤包括在网络设备的端口处接收具有多个字段值的数据报的数据报，解析接收到的数据报以获得字段值，将解析的字段值应用于三元内容可寻址存储器（TCAM），确定匹配 在解析的字段值和TCAM中的预定标准之间，基于所确定的匹配来索引到策略表中，以获得动作条目并基于获得的动作条目采取动作。

公开(公告)号：US5640545A

公开(公告)日：1997-06-17

申请号：US434191

申请日：1995-05-03

申请人： Eric A. Baden ,  Brian A. Childers

发明人： Eric A. Baden ,  Brian A. Childers

IPC分类号： G09G5/393 ,  G06F15/00

CPC分类号： G09G5/393

摘要： An apparatus for transforming pixel data from a data bus into an expected format for storage in a frame buffer has a first multiplexor, a second multiplexor and a controller. The first multiplexor includes two data inputs coupled to the data bus so that the first data input provides pass-through of received data, and the second data input provides end-for-end byte swapping of bus data. Input selection is made by a byte-swap control signal. The second multiplexor includes an output and four data inputs. The output of the first multiplexor is coupled to each of the four inputs of the second multiplexor so as to provide for end-for-end byte swapping from two of the inputs, end-for-end word swapping from another one of the inputs, and end-for-end half-word swapping from a fourth input. The second multiplexor is responsive to a reorder control signal that alternatively selects one of the first, second, third and fourth inputs of the second multiplexor to be gated to the output of the second multiplexor. The controller generates the byte swap control signal and the reorder control signal. Generation of the byte swap control signal is based on an endian-ness characteristic of the data bus. Generation of the reorder control signal is based on a pixel depth of pixel data on the data bus and is based further on a pixel endian-ness type of pixel data on the data bus.

摘要翻译： 用于将来自数据总线的像素数据变换为用于存储在帧缓冲器中的预期格式的装置具有第一多路复用器，第二多路复用器和控制器。 第一多路复用器包括耦合到数据总线的两个数据输入，使得第一数据输入提供接收数据的通过，第二数据输入提供总线数据的端到端字节交换。 输入选择由字节交换控制信号进行。 第二多路复用器包括输出和四个数据输入。 第一多路复用器的输出耦合到第二多路复用器的四个输入中的每一个，以便提供来自两个输入端的端到端字节交换，从另一个输入端进行端对端交换， 以及从第四个输入端到端的半字交换。 第二多路复用器响应重排序控制信号，该信号替代地选择第二多路复用器的第一，第二，第三和第四输入中的一个输入到第二多路复用器的输出。 控制器产生字节交换控制信号和重排序控制信号。 字节交换控制信号的产生基于数据总线的端头特性。 重新排序控制信号的生成基于数据总线上的像素数据的像素深度，并且还基于数据总线上的像素数据类型的像素数据。

公开(公告)号：US08014390B2

公开(公告)日：2011-09-06

申请号：US11289687

申请日：2005-11-30

申请人： Mohan Kalkunte ,  Venkateshwar Buduma ,  Eric A. Baden

发明人： Mohan Kalkunte ,  Venkateshwar Buduma ,  Eric A. Baden

IPC分类号： H04L12/28 ,  H04L12/56 ,  G06F9/00 ,  G06F15/16 ,  G06F17/00

CPC分类号： H04L47/10 ,  H04L45/00 ,  H04L45/742 ,  H04L69/12

摘要： A network device for processing packets. The network device includes applying specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The network device also includes enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The network device further includes outputting means for outputting an address for a matched entry by the memory device and applying means for applying a match from the memory device to an associated entry in a table for applying actions from the table that are associated with the match to the packet.

摘要翻译： 用于处理数据包的网络设备。 网络设备包括将特定字段从分组应用到相关联的存储器设备，以及比较装置，用于将存储器设备的输入与存储器设备中的条目进行比较。 网络设备还包括启用装置，用于允许由存储器设备选择与从输入到存储器设备的位精确匹配的位。 网络设备还包括输出装置，用于输出由存储器装置匹配的条目的地址和应用装置，用于将来自存储器装置的匹配应用于表中的相关条目，用于从与表匹配的表中应用动作 包。

公开(公告)号：US5838955A

公开(公告)日：1998-11-17

申请号：US434197

申请日：1995-05-03

申请人： Brian A. Childers ,  Eric A. Baden

发明人： Brian A. Childers ,  Eric A. Baden

IPC分类号： G06F13/36 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G06F15/16 ,  G06F13/00

CPC分类号： G06F13/36 ,  G09G5/001 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/126

摘要： A system includes a requesting agent coupled to a system bus. The system bus includes an address bus, control lines for indicating a requested transfer type, a data bus, address bus arbitration control lines and data bus arbitration control lines. The system further includes a system bus arbiter coupled to the system bus for resolving competing requests for access to the address bus and for separately resolving competing requests for access to the data bus. A graphics controller for enabling the requesting agent to access a frame buffer has a memory, which may be a FIFO, responsive to a first control signal, for storing data received from a frame buffer. The memory is further responsive to a second control signal for supplying the stored data to the data bus. The graphics controller also includes a controller coupled to the system bus and to the memory means. In response to a frame buffer read request from the requesting agent, the controller initiates a frame buffer read operation in accordance with parameters contained in the received frame buffer read request, and also initiates a request for access to the data bus. The first control signal is generated in response to data associated with the read request becoming available at an output of the frame buffer. The second control signal is generated in response to the requested access to the data bus being granted.

摘要翻译： 系统包括耦合到系统总线的请求代理。 系统总线包括地址总线，用于指示所请求的传送类型的控制线，数据总线，地址总线仲裁控制线和数据总线仲裁控制线。 该系统还包括耦合到系统总线的系统总线仲裁器，用于解决对地址总线访问的竞争性请求，以及用于单独解决对数据总线访问的竞争请求。 用于允许请求代理访问帧缓冲器的图形控制器具有存储器，其可以是响应于第一控制信号的FIFO，用于存储从帧缓冲器接收的数据。 存储器还响应于用于将所存储的数据提供给数据总线的第二控制信号。 图形控制器还包括耦合到系统总线和存储器装置的控制器。 响应于来自请求代理的帧缓冲器读请求，控制器根据包含在接收到的帧缓冲器读请求中的参数启动帧缓冲器读操作，并且还启动对数据总线的访问请求。 响应于与在帧缓冲器的输出处可用的读请求相关联的数据产生第一控制信号。 第二控制信号是响应所请求的访问数据总线而被产生的。

公开(公告)号：US5689656A

公开(公告)日：1997-11-18

申请号：US767118

申请日：1997-01-10

申请人： Eric A. Baden ,  Brian A. Childers

发明人： Eric A. Baden ,  Brian A. Childers

IPC分类号： G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362

摘要： A method of prioritizing computer resource access requests to a shared computer resource, such as a video frame buffer, includes the steps of providing a number, n, of priority schemes in correspondence with a like number of potentially requesting entities, where n is an integer greater than one, and where each priority scheme designates relative priority of the potentially requesting entities with respect to one another. Thus, for each priority scheme there exists one corresponding potentially requesting entity, and a number, n-1, of noncorresponding potentially requesting entities. Next, one of the priority schemes is selected for use as a current priority scheme. A set of currently requesting entities is then determined from the number of potentially requesting entities, and the current priority scheme is used to select a highest priority requesting entity from the set of currently requesting entities. Finally, one of the priority schemes is newly selected as the current priority scheme, wherein the newly selected priority scheme corresponds to the highest priority requesting entity. In one embodiment, at least one of the priority schemes designates a first priority for the corresponding potentially requesting entity, and a second priority for one of the noncorresponding potentially requesting entities, where the first priority is higher than the second priority. In another aspect of the invention, at least one of the potentially requesting entities has a same relative priority designation in at least two of the n priority schemes.

摘要翻译： 一种将计算机资源访问请求划分为诸如视频帧缓冲器的共享计算机资源的方法包括以下步骤：与相似数量的潜在请求实体相对应地提供数量为n的优先级方案，其中n是整数 大于1，并且其中每个优先级方案指定潜在请求实体相对于彼此的相对优先级。 因此，对于每个优先级方案，存在一个对应的潜在请求实体和数个n-1个不相应的潜在请求实体。 接下来，选择优先级方案之一用作当前优先级方案。 然后从潜在请求实体的数量确定一组当前请求实体，并且使用当前优先级方案从当前请求实体的集合中选择最高优先级请求实体。 最后，新选择其中一个优先级方案作为当前优先级方案，其中新选择的优先级方案对应于最高优先级请求实体。 在一个实施例中，至少一个优先级方案指定对应的潜在请求实体的第一优先级，以及第一优先级高于第二优先级的非相应潜在请求实体之一的第二优先级。 在本发明的另一方面，至少一个潜在请求实体在n个优先级方案中的至少两个中具有相同的相对优先级指定。

公开(公告)号：US5634013A

公开(公告)日：1997-05-27

申请号：US434183

申请日：1995-05-03

申请人： Brian A. Childers ,  Eric A. Baden

发明人： Brian A. Childers ,  Eric A. Baden

IPC分类号： G06F12/04 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F12/04 ,  G06F13/4013 ,  G06F13/4018

摘要： A computer bus bridge interconnects first and second buses, the first bus being big-endian and the second bus being little-endian. First address and size signals received from the first bus during a first bus cycle are converted into second address and data unit enable signals for transmission on the second bus during a second bus cycle. The first address comprises a low-order address portion and a remaining upper-order address portion. The data unit enable signals are generated from the low-order address portion and the size signals of the first bus. An address offset is generated from the data unit enable signals. The remaining upper-order address portion of the first address are then concatenated with the address offset and a predetermined lower address portion for use as the second address. The data unit enable signals may designate, say, up to 4 possible data bytes being transferred during a single beat on the second bus. The size signals may designate, say, up to 8 possible contiguous data units being transferred during a single beat on the first bus. Here, byte enable signals are generated by first generating 8 temporary byte enable signals from the low-order address portion and the size signals. Then, 4 of the 8 temporary byte enable signals are selected for use as the byte enable signals on the second bus. The address offset is generated based on presence or absence of assertion of 4 lowest order ones of the 8 temporary byte enable signals.

摘要翻译： 计算机总线桥连接第一和第二总线，第一个总线是大端，第二个总线是小端。 在第一总线周期期间从第一总线接收的第一地址和大小信号在第二总线周期期间被转换为第二地址和数据单元使能信号用于在第二总线上传输。 第一地址包括低位地址部分和剩余的高阶地址部分。 数据单元使能信号从低位地址部分和第一总线的大小信号产生。 从数据单元使能信号产生地址偏移。 然后将第一地址的剩余高阶地址部分与地址偏移量和预定的较低地址部分连接以用作第二地址。 数据单元使能信号可以指定在第二总线上的单个节拍期间传输的多达4个可能的数据字节。 尺寸信号可以指定在第一总线上的单次拍击期间传输的多达8个可能的连续数据单元。 这里，通过首先从低阶地址部分和尺寸信号产生8个临时字节使能信号来产生字节使能信号。 然后，8个临时字节使能信号中的4个被选择用作第二总线上的字节使能信号。 基于8个临时字节使能信号中4个最低位的有效断言产生地址偏移。

公开(公告)号：US5625778A

公开(公告)日：1997-04-29

申请号：US434193

申请日：1995-05-03

申请人： Brian A. Childers ,  Eric A. Baden

发明人： Brian A. Childers ,  Eric A. Baden

IPC分类号： G06F13/16 ,  G06F13/14

CPC分类号： G06F13/1642

摘要： A system has a system resource, such as a frame buffer, coupled to a system bus, the system bus conveying a request for access to the system resource from another system element connected to the system bus. An apparatus for presenting the access request to the system resource from the system bus includes a queue, a multiplexor that is preferably glitchless, and a controller. The queue has an input for receiving access request information from the system bus; one or more storage elements, each for storing access request information, wherein the one or more storage means are connected to form a queue having a head and a tail; and a queue output for supplying data stored in the head of the queue. The multiplexor has a first input coupled to the queue output, a second input for receiving the access request information from the system bus, and a multiplexor output for supplying the access request to the system resource. The controller is coupled to the queue and to the multiplexor, for initiating the loading of the access request information into the queue, and for initially causing the multiplexor to supply, at the multiplexor output, the access request information from the second input, and for subsequently causing, after the access request information becomes available at the queue output, the multiplexor to supply, at the multiplexor output, the access request information from the first input. This configuration reduces latency on read operations to the frame buffer.

摘要翻译： 系统具有耦合到系统总线的系统资源，例如帧缓冲器，系统总线从连接到系统总线的另一系统元件传送对系统资源的访问请求。 用于从系统总线向系统资源呈现访问请求的装置包括队列，优选无毛刺的多路复用器和控制器。 队列具有用于从系统总线接收访问请求信息的输入; 一个或多个存储元件，每个用于存储访问请求信息，其中所述一个或多个存储装置被连接以形成具有头部和尾部的队列; 以及用于提供存储在队列头部中的数据的队列输出。 多路复用器具有耦合到队列输出的第一输入端，用于从系统总线接收访问请求信息的第二输入端和用于向系统资源提供访问请求的多路复用器输出端。 控制器耦合到队列和多路复用器，用于启动将访问请求信息加载到队列中，并且为了最初使多路复用器在多路复用器输出端提供来自第二输入的访问请求信息，并且为 在所述访问请求信息在所述队列输出可用时，所述多路复用器在所述多路复用器输出时提供来自所述第一输入的访问请求信息。 此配置减少了对帧缓冲区的读取操作的延迟。