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    Use of periodic refresh in medium retention memory arrays
    1.
    发明授权
    Use of periodic refresh in medium retention memory arrays 有权
    在介质保留存储器阵列中使用定期更新

    公开(公告)号：US07474579B2

    公开(公告)日：2009-01-06

    申请号：US11613832

    申请日：2006-12-20

    申请人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

    发明人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431

    摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

    摘要翻译： 公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法 跟踪元件的电阻已达到或超过预定参考阈值电阻值。 跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元 在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

    USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS
    2.
    发明申请
    USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS 有权
    在中继记忆阵列中使用周期性刷新

    公开(公告)号：US20080151669A1

    公开(公告)日：2008-06-26

    申请号：US11613832

    申请日：2006-12-20

    申请人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

    发明人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431

    摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

    摘要翻译： 公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法 跟踪元件的电阻已达到或超过预定参考阈值电阻值。 跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元 在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

    Architecture for generating adaptive arbitrary waveforms
    3.
    发明授权
    Architecture for generating adaptive arbitrary waveforms 失效
    用于生成自适应任意波形的体系结构

    公开(公告)号：US07072781B1

    公开(公告)日：2006-07-04

    申请号：US10885284

    申请日：2004-07-06

    申请人： Eugen Gershon ,  David Gaun ,  Colin S. Bill ,  Tzu-Ning Fang

    发明人： Eugen Gershon ,  David Gaun ,  Colin S. Bill ,  Tzu-Ning Fang

    IPC分类号： G01R31/36

    CPC分类号： G01R31/31924 ,  G01R31/3167 ,  G01R31/31908 ,  G11C29/56 ,  G11C29/56004

    摘要： A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.

    摘要翻译： 具有反馈回路的测试系统，其根据改变的DUT / CUT参数，有助于将DUT / CUT（被测设备/待测电路）的输出测试波形实时调整。 该系统包括具有任意波形发生器（AWG）的测试器和监视DUT / CUT的状态的数据采集系统（DAS）。 AWG和DAS通过反馈回路连接到DUT / CUT，AWG将测试波形输出到DUT / CUT，DAS监视DUT / CUT参数，DAS分析并传送AWG的变化，以实现更改 输出波形。 AWG通过选择和校准过程组装在一起的小片（或片段）中构建输出波形。 反馈架构有助于输出波形的一些变化，包括预先组装的切片的原始顺序的改变以及输出波形的幅度/形状的变化。

    Variable breakdown characteristic diode
    5.
    发明授权
    Variable breakdown characteristic diode 有权
    可变击穿特性二极管

    公开(公告)号：US07579631B2

    公开(公告)日：2009-08-25

    申请号：US11087000

    申请日：2005-03-22

    申请人： David Gaun ,  Colin S. Bill ,  Swaroop Kaza

    发明人： David Gaun ,  Colin S. Bill ,  Swaroop Kaza

    IPC分类号： H01L29/00

    CPC分类号： H01L51/0575 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5692 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/11 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/285

    摘要： A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an applied electric field, is imposed upon the first and second electrode, ions move and dope and/or de-dope the polymer. The applied external stimuli used to dope the polymer is larger than an applied external stimuli to operate the memory cell. The polymer functions as a variable breakdown characteristic diode with electrical characteristics which are a consequence of the doping degree. The memory element may have a current limited read signal. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers, hand-held electronic devices and memory devices containing the memory cell(s) are also disclosed.

    摘要翻译： 公开了一种由在至少两个电极之间具有可控导电介质的至少两个电极制成的存储单元。 可控导电介质包括由超离子材料和有源层制成的钝化层。 当诸如施加的电场的外部刺激施加在第一和第二电极上时，离子移动并掺杂和/或去透明聚合物。 用于掺杂聚合物的应用外部刺激物大于施加的外部刺激以操作记忆单元。 该聚合物用作具有电特性的可变击穿特性二极管，这是掺杂度的结果。 存储元件可以具有电流受限读取信号。 还公开了制造存储器件/单元的方法，使用存储器件/单元的方法，以及诸如计算机，手持式电子设备和包含存储单元的存储器件的设备。

    Memory element using active layer of blended materials
    7.
    发明授权
    Memory element using active layer of blended materials 有权
    记忆元素使用有源层的混合材料

    公开(公告)号：US07378682B2

    公开(公告)日：2008-05-27

    申请号：US11052688

    申请日：2005-02-07

    申请人： David Gaun ,  Swaroop Kaza ,  Stuart Spitzer ,  Juri Krieger ,  Richard Kingsborough

    发明人： David Gaun ,  Swaroop Kaza ,  Stuart Spitzer ,  Juri Krieger ,  Richard Kingsborough

    IPC分类号： H01L51/00

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016

    摘要： The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for receiving a charged specie from the passive layer. The active layer is a mixture of (i) a first polymer, and (ii) a second polymer for enhancing ion transport, improving the interface and promoting a rapid and substantially uniform distribution of the charged specie in the active layer, i.e., preventing a localized injection of the charged species. These features result in a memory element with improved stability, a more controllable ON-state resistance, improved switching speed and a lower programming voltage.

    摘要翻译： 本存储器件具有第一和第二电极，在第一和第二电极之间并且与第一电极接触并且与第一电极接触的无源层以及在第一和第二电极之间并且与被动层和第二电极接触的有源层 电极，用于从被动层接收带电物质。 活性层是（i）第一聚合物和（ii）用于增强离子迁移的第二聚合物的混合物，改善界面并促进活性层中带电物质的快速且基本上均匀的分布，即防止 局部注射带电物种。 这些特征导致存储元件具有改进的稳定性，更可控的导通电阻，改进的开关速度和较低的编程电压。

    Polymer memory cell operation
    9.
    发明授权
    Polymer memory cell operation 有权
    聚合物记忆体操作

    公开(公告)号：US07221599B1

    公开(公告)日：2007-05-22

    申请号：US10978621

    申请日：2004-11-01

    申请人： David Gaun ,  Juri H Krieger ,  Stuart Spitzer

    发明人： David Gaun ,  Juri H Krieger ,  Stuart Spitzer

    IPC分类号： G11C7/10

    CPC分类号： G11C7/20 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2013/0083

    摘要： Systems and methodologies are provided for activating a polymer memory cell(s) after production by subjecting the polymer memory cell to an electrical field, for an initialization thereof. Such initialization can facilitate the distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell. The memory cell can include various layers of alternating passive and active media, which are sandwiched between conducting electrode layers.

    摘要翻译： 提供了系统和方法，用于通过使聚合物存储单元经受电场来进行初始化来激活生产后的聚合物存储单元。 这种初始化可以促进聚合物存储单元的活性层内的金属离子（或带电的金属分子）的分布和迁移率。 存储单元可以包括夹在导电电极层之间的交替的被动和有源介质的各种层。