Motherboard having a non-volatile memory which is reprogrammable through a video display port and a non-volatile memory switchable between two communication protocols
    1.
    发明授权
    Motherboard having a non-volatile memory which is reprogrammable through a video display port and a non-volatile memory switchable between two communication protocols 有权
    主板具有可通过视频显示端口重新编程的非易失性存储器和可在两个通信协议之间切换的非易失性存储器

    公开(公告)号:US07069371B2

    公开(公告)日:2006-06-27

    申请号:US10798485

    申请日:2004-03-10

    IPC分类号: G06F13/14 G06F13/00

    CPC分类号: G06F13/4243

    摘要: A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

    摘要翻译: 计算机系统的主板具有视频显示端口,可再编程非易失性存储器,用于非易失性存储器的控制器,以及用于向视频显示端口输出视频信号的图形控制器电路。 有线电路将图形控制器电路连接到控制器到端口。 因此,可以使用视频显示端口将来自计算机系统的视频信号输出到外围视频显示装置,并且视频显示端口可以用作输入端口以重新编程非易失性存储器。 本发明还涉及一种具有非易失性存储器单元阵列和用于与其通信的两个端口的非易失性存储器件。 第一端口接收第一通信协议并与第一通信协议中的阵列接口。 第二端口接收第二通信协议并将第二通信协议转换为第一通信协议。

    Motherboard having a non-volatile memory which is reprogrammable through a video display port and a non-volatile memory switchable between two communication protocols
    2.
    发明申请
    Motherboard having a non-volatile memory which is reprogrammable through a video display port and a non-volatile memory switchable between two communication protocols 有权
    主板具有可通过视频显示端口重新编程的非易失性存储器和可在两个通信协议之间切换的非易失性存储器

    公开(公告)号:US20050200628A1

    公开(公告)日:2005-09-15

    申请号:US10798485

    申请日:2004-03-10

    IPC分类号: G06F13/00

    CPC分类号: G06F13/4243

    摘要: A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

    摘要翻译: 计算机系统的主板具有视频显示端口,可再编程非易失性存储器,用于非易失性存储器的控制器,以及用于向视频显示端口输出视频信号的图形控制器电路。 有线电路将图形控制器电路连接到控制器到端口。 因此,可以使用视频显示端口将来自计算机系统的视频信号输出到外围视频显示装置,并且视频显示端口可以用作输入端口以重新编程非易失性存储器。 本发明还涉及一种具有非易失性存储器单元阵列和用于与其通信的两个端口的非易失性存储器件。 第一端口接收第一通信协议并与第一通信协议中的阵列接口。 第二端口接收第二通信协议并将第二通信协议转换为第一通信协议。

    Motherboard having a non-volatile memory which is reprogrammable through a video display port
    3.
    发明授权
    Motherboard having a non-volatile memory which is reprogrammable through a video display port 有权
    主板具有通过视频显示端口可重新编程的非易失性存储器

    公开(公告)号:US07146442B2

    公开(公告)日:2006-12-05

    申请号:US11407601

    申请日:2006-04-19

    IPC分类号: G06F13/00 G06F3/00

    CPC分类号: G06F13/4243

    摘要: A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

    摘要翻译: 计算机系统的主板具有视频显示端口,可再编程非易失性存储器,用于非易失性存储器的控制器,以及用于向视频显示端口输出视频信号的图形控制器电路。 有线电路将图形控制器电路连接到控制器到端口。 因此,可以使用视频显示端口将来自计算机系统的视频信号输出到外围视频显示装置,并且视频显示端口可以用作输入端口以重新编程非易失性存储器。 本发明还涉及一种具有非易失性存储器单元阵列和用于与其通信的两个端口的非易失性存储器件。 第一端口接收第一通信协议并与第一通信协议中的阵列接口。 第二端口接收第二通信协议并将第二通信协议转换为第一通信协议。

    Motherboard having a non-volatile memory which is reprogrammable through a video display port

    公开(公告)号:US20060190646A1

    公开(公告)日:2006-08-24

    申请号:US11407601

    申请日:2006-04-19

    IPC分类号: G06F13/00

    CPC分类号: G06F13/4243

    摘要: A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the graphics controller circuit to the controller to the port. Thus, the video display port can be used to output video signals from the computer system to a peripheral video display device, and the video display port can be used as an input port to reprogram the non-volatile memory. The present invention also relates to a non-volatile memory device which has an array of non-volatile memory cells and two ports for communication therewith. A first port receives a first communication protocol and interfaces with the array in the first communication protocol. A second port receives a second communication protocol and converts the second communication protocol into the first communication protocol.

    Macro cell for integrated circuit physical layer interface
    9.
    发明申请
    Macro cell for integrated circuit physical layer interface 有权
    宏单元用于集成电路物理层接口

    公开(公告)号:US20050229132A1

    公开(公告)日:2005-10-13

    申请号:US10810294

    申请日:2004-03-26

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5045

    摘要: A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with the IO buffer cells in the interface portion. The macro cell also includes an interface definition having a plurality of interface IO signal nets, which are routed to corresponding ones of the plurality of macro cell signal slots. The macro cell is adapted to be instantiated as a unit in the integrated circuit design.

    摘要翻译: 为具有输入 - 输出(IO)区域的集成电路设计提供宏单元,所述输入 - 输出(IO)区域具有与IO区域的接口部分的IO槽中的其它单元物理分散的多个IO缓冲单元。 宏小区包括物理分散以便与接口部分中的IO缓冲单元基本对齐的多个宏小区IO信号时隙。 宏小区还包括具有多个接口IO信号网络的接口定义,其被路由到多个宏小区信号时隙中的相应的一个。 宏单元适于在集成电路设计中被实例化为单元。

    Low power set associative cache memory
    10.
    发明授权
    Low power set associative cache memory 失效
    低功耗组相关缓存存储器

    公开(公告)号:US5913223A

    公开(公告)日:1999-06-15

    申请号:US8206

    申请日:1993-01-25

    IPC分类号: G06F12/08

    摘要: A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus.

    摘要翻译: 提供了具有高速缓存数据RAM(30)和标签RAM(28)的四路缓存数据存储器。 标签RAM(28)能够访问其中的一个标签。 该标签与接收到的存储器地址的标签部分进行比较,以确定标签是否存储在其中。 如果真正的比较结果,则指示HIT,并且这用于启用缓存数据RAM(30)的一部分。 然后在数据总线上输出使能部分中的数据。