公开(公告)号：US06483744B2

公开(公告)日：2002-11-19

申请号：US09887904

申请日：2001-06-21

Applicant: Eun-Cheol Kim ,  Yeong-Taek Lee

Inventor： Eun-Cheol Kim ,  Yeong-Taek Lee

IPC: G11C1604

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/24

Abstract: A non-volatile semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of bitlines and wordlines, each memory cell being programmed to one of plurality of data storage states. A node is connected to a selected bitline responsive to a storage state in a selected memory cell. A plurality of latched registers is connected to the node to store and output data bits corresponding the storage state, the data bits being assigned to the selected bitline. A circuit is adapted to precharge the selected bitline before sensing the selected memory cell and is adapted to equalize the selected bitline and the node after sensing the selected memory cell.

Abstract translation: 一种非易失性半导体存储器件，包括具有耦合到多个位线和字线的多个存储器单元的存储单元阵列，每个存储器单元被编程为多个数据存储状态之一。 响应于所选存储器单元中的存储状态，节点连接到选定的位线。 多个锁存寄存器连接到节点以存储和输出与存储状态相对应的数据位，数据位被分配给所选择的位线。 电路适于在感测所选择的存储器单元之前对所选位线进行预充电，并且适于在感测所选择的存储器单元之后均衡所选择的位线和节点。

公开(公告)号：US06031785A

公开(公告)日：2000-02-29

申请号：US39782

申请日：1998-03-16

Applicant: Hee-Choul Park ,  Eun-Cheol Kim

Inventor： Hee-Choul Park ,  Eun-Cheol Kim

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1018

Abstract: A burst SRAM device is provided having a burst column selection circuit which is activated in accordance with a burst address, in addition to a column selection circuit for selecting columns of a memory cell array capable of storing a binary data. An internal column address portion of an external column address is applied to the column selection circuit as a first burst address signal. The column selection circuit selects at the same time at least two columns in response to the first burst address signal. During a burst read mode, at least two columns are simultaneously selected in response to the first burst address signal, and data stored in the selected cells are simultaneously sensed and amplified by at least two sense amplifiers corresponding to the selected memory cells. The data amplified thus are stored in a data output register. The burst addresses are applied to the burst column selection circuit. The burst column selection circuit allows the data stored in the data output register to be sequentially delivered to input/output data line pair in response to the burst addresses. As a result, an interval between a generation time of the first burst address and the time, which takes for a sensing operation of the last 1-bit data to be completed by the last burst address, can be considerably shortened as compared with the conventional device. During a burst write mode, at least two columns are simultaneously selected by the first burst address, and 1-bit data from the input/output data line pair corresponding to locations of the first burst address of the data input register are stored. The burst column selection circuit allows the data delivered sequentially from the data line pair to be sequentially stored in regions of the other burst addresses of the data input register in response to the other burst addresses. At least 2-bit data stored in the data input register are sequentially or simultaneously written in the selected memory cells of the selected columns.

公开(公告)号：US06307412B1

公开(公告)日：2001-10-23

申请号：US09323590

申请日：1999-06-01

Applicant: Eun-Cheol Kim ,  Kook-Hwan Kwon

Inventor： Eun-Cheol Kim ,  Kook-Hwan Kwon

IPC: H03K501

CPC classification number: G11C7/225 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2227 ,  H03K5/13 ,  H03K5/15 ,  H03K5/19

Abstract: A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

Abstract translation: 时钟监视电路包括分别接收时钟信号和反相时钟信号的第一和第二延迟和时钟信号产生单元。 第一和第二延迟和时钟信号产生单元分别产生第一和第二信号。 逻辑和单元对第一和第二信号进行逻辑加和，以产生停止时钟信号。 根据本发明的时钟监控电路可以监视时钟信号的存在，而与时钟信号的操作周期无关。 此外，利用根据本发明的时钟监视电路的同步半导体存储器件仅在存在时钟信号时才消耗电流。 也就是说，当不存在时钟信号时，该装置不消耗电流，从而在待机模式下减少不必要的电力浪费。

公开(公告)号：US6023177A

公开(公告)日：2000-02-08

申请号：US988312

申请日：1997-12-11

Applicant: Eun-Cheol Kim ,  Chul-Min Jung

Inventor： Eun-Cheol Kim ,  Chul-Min Jung

IPC: G11C11/407 ,  G06F12/02 ,  G11C7/10 ,  G11C11/41 ,  G11C11/413 ,  H03L7/00

CPC classification number: G11C7/1072 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/1078

Abstract: A semiconductor memory device for providing a burst mode control signal. The semiconductor memory device includes a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal, a plurality of transition registers for respectively changing the driving signal in synchronization with a first edge of a clock signal to generate changed driving signals, and a second logic circuit for generating the burst mode control signal generated by the logic combination of the changed driving signals in response to a read latency control signal.

Abstract translation: 一种用于提供突发模式控制信号的半导体存储器件。 半导体存储器件包括：第一逻辑电路，用于响应于外部输入的写入和读取控制信号和外部输入的芯片使能信号的第一逻辑电平产生驱动信号;多个转换寄存器，用于分别改变驱动信号 与时钟信号的第一边沿同步以产生改变的驱动信号;以及第二逻辑电路，用于响应于读等待时间控制信号而产生由所改变的驱动信号的逻辑组合产生的突发模式控制信号。

公开(公告)号：US09257195B2

公开(公告)日：2016-02-09

申请号：US14309959

申请日：2014-06-20

Applicant: Eun-Chu Oh ,  Eun-Cheol Kim ,  Jun-Jin Kong ,  Kwang-Hoon Kim ,  Hong-Rak Son

Inventor： Eun-Chu Oh ,  Eun-Cheol Kim ,  Jun-Jin Kong ,  Kwang-Hoon Kim ,  Hong-Rak Son

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0409

Abstract: A method of operating a memory controller in a memory system including a nonvolatile memory device includes; erasing memory cells of a target memory block of the non-volatile memory device on a block basis, and then searching for a bad memory cell by a performing an erase verifying operation, comparing a threshold voltage of the bad memory cell to a reference voltage to generate comparison results, and designating as a bad area one of the entire target memory block, and a sub-block of the target memory block in response to the comparison results.

Abstract translation: 一种在包括非易失性存储器件的存储器系统中操作存储器控制器的方法包括： 以块为单位擦除非易失性存储器件的目标存储块的存储单元，然后通过执行擦除验证操作来搜索不良存储单元，将坏存储单元的阈值电压与参考电压进行比较，以 生成比较结果，并且根据比较结果将整个目标存储器块中的一个指定为不良区域，以及目标存储器块的子块。

公开(公告)号：US06356504B1

公开(公告)日：2002-03-12

申请号：US09653442

申请日：2000-09-01

Applicant: Eun-Cheol Kim

Inventor： Eun-Cheol Kim

IPC: G11C800

CPC classification number: G11C7/1066 ,  G11C7/1018 ,  G11C7/1045 ,  G11C8/10 ,  G11C11/4082 ,  G11C11/4087

Abstract: A burst-type random access memory device according to the present invention includes an address generator that receives an initial address to generate a sequence of burst addresses according to either one of a single data rate mode and a double data rate mode. A decoding circuit decodes the burst address thus generated. Therefore, in the memory device are automatically generated a sequence of burst addresses necessary for a sequential/interleaved burst operation of the single data rate mode and the double data rate mode.

Abstract translation: 根据本发明的突发式随机存取存储器件包括地址发生器，其接收根据单个数据速率模式和双倍数据速率模式中的任何一个的初始地址以产生脉冲串地址序列。 解码电路对由此产生的脉冲串地址进行解码。 因此，在存储装置中，自动产生单个数据速率模式和双数据速率模式的顺序/交错突发操作所需的脉冲串地址序列。

公开(公告)号：US06335881B2

公开(公告)日：2002-01-01

申请号：US09781932

申请日：2001-02-12

Applicant: Jong-Hwa Kim ,  Eun-Cheol Kim

Inventor： Jong-Hwa Kim ,  Eun-Cheol Kim

IPC: G11C1604

CPC classification number: G11C16/34 ,  G11C16/12

Abstract: The method for programming a flash memory device includes sequentially loading program data in the page buffer circuit responsive to a first command signal, the first command signal indicating program data input and generating a program voltage responsive to a second command signal, the second command signal indicating programming initiation. EEPROM cells are programmed after the program voltage reaches a predetermined target. All of the programmed EEPROM cells are verified to ensure that they are properly programmed. If the EEPROM cells are not properly programmed, programming is repeated until all of the EEPROM cells are properly programmed. The program voltage is increased in a stepwise manner every time programming is repeated.

Abstract translation: 用于对闪速存储器件进行编程的方法包括响应于第一命令信号顺序地将程序数据加载到页缓冲器电路中，第一命令信号指示程序数据输入并响应于第二命令信号产生编程电压，第二命令信号指示 编程启动。 在程序电压达到预定目标之后，对EEPROM单元进行编程。 验证所有编程的EEPROM单元，以确保它们被正确编程。 如果EEPROM单元未正确编程，则重复编程，直到所有EEPROM单元都被正确编程。 每当重复编程时，逐步地增加编程电压。