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    Stacked semiconductor device and related method
    4.
    发明授权
    Stacked semiconductor device and related method 有权
    叠层半导体器件及相关方法

    公开(公告)号：US07682450B2

    公开(公告)日：2010-03-23

    申请号：US11485323

    申请日：2006-07-13

    申请人： Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

    发明人： Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

    IPC分类号： C30B21/02

    CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

    摘要翻译： 公开了一种叠层半导体器件及其制造方法。 堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅，以及填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部， 并且上部部分与基板成锥形。 层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

    Stacked semiconductor device and related method
    5.
    发明授权
    Stacked semiconductor device and related method 有权
    叠层半导体器件及相关方法

    公开(公告)号：US08419853B2

    公开(公告)日：2013-04-16

    申请号：US12623515

    申请日：2009-11-23

    申请人： Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

    发明人： Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

    IPC分类号： C30B21/04

    CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

    摘要翻译： 公开了一种叠层半导体器件及其制造方法。 堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅和填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部， 并且上部部分与基板成锥形。 层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

    Stacked semiconductor device and related method
    6.
    发明申请
    Stacked semiconductor device and related method 有权
    叠层半导体器件及相关方法

    公开(公告)号：US20070023794A1

    公开(公告)日：2007-02-01

    申请号：US11485323

    申请日：2006-07-13

    申请人： Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

    发明人： Yun-Seung Kang ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim ,  Suk-Chul Bang

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

    摘要翻译： 公开了一种叠层半导体器件及其制造方法。 堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅和填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部， 并且上部部分与基板成锥形。 层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

    Method of fabricating CMOS transistor that prevents gate thinning
    7.
    发明授权
    Method of fabricating CMOS transistor that prevents gate thinning 有权
    制造防止栅极薄化的CMOS晶体管的方法

    公开(公告)号：US07268029B2

    公开(公告)日：2007-09-11

    申请号：US10994042

    申请日：2004-11-19

    申请人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    发明人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/31111 ,  H01L21/31144

    摘要： Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

    摘要翻译： 提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。 使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。 如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由 构图多晶硅层。 用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

    Method of fabricating CMOS transistor that prevents gate thinning
    8.
    发明申请
    Method of fabricating CMOS transistor that prevents gate thinning 有权
    制造防止栅极薄化的CMOS晶体管的方法

    公开(公告)号：US20050112814A1

    公开(公告)日：2005-05-26

    申请号：US10994042

    申请日：2004-11-19

    申请人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    发明人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    IPC分类号： H01L21/311 ,  H01L21/8238 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/8234 ,  H01L21/84

    CPC分类号： H01L21/823842 ,  H01L21/31111 ,  H01L21/31144

    摘要： Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

    摘要翻译： 提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。 使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。 如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由 构图多晶硅层。 用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

    METHODS OF FORMING SEMICONDUCTOR DEVICES USING SELF-ALIGNED METAL SHUNTS
    10.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES USING SELF-ALIGNED METAL SHUNTS 审中-公开
    使用自对准金属层形成半导体器件的方法

    公开(公告)号：US20080176374A1

    公开(公告)日：2008-07-24

    申请号：US12018469

    申请日：2008-01-23

    申请人： Yeol Jon ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim

    发明人： Yeol Jon ,  Eun-Kuk Chung ,  Joon Kim ,  Jin-Hong Kim

    IPC分类号： H01L21/336 ,  H01L21/768

    CPC分类号： H01L21/823437 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/11 ,  H01L29/66545

    摘要： A method of fabricating a semiconductor device using a self-aligned metal shunt process is disclosed. The method can include sequentially forming a lower conductive pattern and a sacrificial pattern on a semiconductor substrate. An interlayer dielectric layer is formed to cover the sacrificial pattern. The interlayer dielectric layer is patterned to form a preliminary trench that exposes the top surface of the sacrificial pattern. The exposed sacrificial pattern is removed to form a trench that expose the top surface of the lower conductive pattern. An upper conductive pattern is formed to fill the trench.

    摘要翻译： 公开了使用自对准金属分流工艺制造半导体器件的方法。 该方法可以包括在半导体衬底上顺序地形成下导电图案和牺牲图案。 形成层间电介质层以覆盖牺牲图案。 图案化层间电介质层以形成暴露牺牲图案的顶表面的预备沟槽。 去除暴露的牺牲图案以形成暴露下导电图案的顶表面的沟槽。 形成上部导电图案以填充沟槽。