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公开(公告)号：US5329481A
公开(公告)日：1994-07-12
申请号：US989629
申请日：1992-12-14
IPC分类号： H01L21/8247 , G11C11/34 , H01L21/8229 , H01L27/102 , H01L27/115
CPC分类号： G11C11/34
摘要： A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).
摘要翻译： 一种具有至少一个可编程存储单元的半导体器件，其包括具有第一导电类型的发射极（11）和集电极（12）的双极晶体管（T1）和具有第二导电类型的第二基极（10）。 发射极（11）和集电极（12）分别耦合到第一电源线（100）和第二供电线（200）。 基极（10）通过控制晶体管（T2）耦合到写入装置（WRITE）。 读取装置（READ）包括在第一电源线（100）和第二电源线（200）之间延伸的电流路径（I）中，并且包括发射器（11）和集电极（12）之间的电流路径。 在优选实施例中，收集器（12）还经由可切换负载（T5）耦合到第二供电管线（200）。
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公开(公告)号：US20100176868A1
公开(公告)日：2010-07-15
申请号：US12676914
申请日：2008-09-09
IPC分类号： H03K17/687
CPC分类号： H03K19/018528 , G11C27/026
摘要： The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages. The transistor element is configured such that in case a differential voltage between the first predefined alternating voltage and the second predefined alternating voltage is higher than the predefined threshold voltage and the first switching unit is not conductive the third terminal is charged with the first predefined alternating voltage.
摘要翻译： 本申请涉及一种包括具有至少三个端子的第一晶体管元件和至少一个开关单元的装置。 本申请还涉及一种其上存储有计算机程序的计算机可读介质和包括该装置的跟踪和保持电路的方法。 该装置包括具有至少三个端子的第一晶体管元件，其中第一端子被提供有第一电压，并且其中第二端子被提供有第二电压。 该装置包括第一开关单元，其中第三端子经由第一开关单元连接到地电位。 晶体管元件包括预定义的阈值电压。 第一电压和第二电压是预定的交流电压。 晶体管元件被配置为使得在第一预定交流电压和第二预定交流电压之间的差分电压高于预定阈值电压并且第一开关单元不导通的情况下，第三端子被充电第一预定交流电压 。
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3.发明授权Resistor network such as a resistor ladder network and a method for manufacturing such a resistor network 有权电阻网络如电阻梯形网络以及制造这种电阻网络的方法公开(公告)号：US07737817B2
公开(公告)日：2010-06-15
申请号：US10517106
申请日：2003-05-21
IPC分类号： H01C7/22
CPC分类号： H01L27/0802
摘要： The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.
摘要翻译： 本发明涉及一种电阻网络（2），例如电阻梯形网络，至少包括一个电阻体（4），该电阻器体（4）至少设置有位于第一抽头和第二抽头之间的抽头（6）的至少一列 抽头，其中在使用中，至少两个抽头可以与相应的第一和第二参考输入电位源连接，并且其中所述至少一列抽头的每个抽头可以用于经由接触区域输出输出电位，所述接触区域 与所述有关抽头连接，其中所述电阻体（4）包括多个电阻子体（5），其中每个电阻子体（5）与抽头（8）的列（6）连接，以及 其中通过与电阻子体（5）连接的抽头（8）的电连接来建立电阻子体（5）之间的唯一电连接。 此外，本发明涉及一种用于制造诸如电阻梯形网络的电阻网络（2）的方法。
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公开(公告)号：US20090164699A1
公开(公告)日：2009-06-25
申请号：US12296150
申请日：2007-02-15
申请人： Pim Tuyls , Maarten Vertregt , Hans De Jong , Frans List , Mathias Wagner , Frank Zachariasse , Arjan Mels
发明人： Pim Tuyls , Maarten Vertregt , Hans De Jong , Frans List , Mathias Wagner , Frank Zachariasse , Arjan Mels
IPC分类号： G06F12/00
CPC分类号： G06F21/556 , H04L9/0877
摘要： It is described a method for providing an electronic key within an integrated circuit (100) including both a volatile memory (102) and a non-volatile memory (104). The described comprises starting up the integrated circuit (100), reading the logical state of predetermined data storage cells (102a) assigned to the volatile memory (102), which data storage cells (102a) are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (102a). Preferably, the predetermined data storage cells (102a) are randomly distributed within the volatile memory (102). It is further described an integrated circuit (100) for providing an electronic key. The integrated circuit (100) comprises a volatile memory (102) comprising predetermined data storage cells (102a), which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and a non-volatile memory (104) having information stored upon regarding the predetermined data storage cells (102a). Thereby, the electronic key is defined by the corresponding logical states of the predetermined data storage cells (102a).
摘要翻译： 描述了在包括易失性存储器（102）和非易失性存储器（104）的集成电路（100）内提供电子钥匙的方法。 所描述的包括启动集成电路（100），读取分配给易失性存储器（102）的预定数据存储单元（102a）的逻辑状态，哪个数据存储单元（102a）的特征在于具有多个启动过程 它们分别采用相同的逻辑状态，并且通过使用预定数据存储单元（1022）的逻辑状态来生成电子密钥。 优选地，预定数据存储单元（102a）被随机分布在易失性存储器（102）内。 进一步描述了用于提供电子钥匙的集成电路（100）。 集成电路（100）包括包括预定数据存储单元（102）的易失性存储器（102），其特征在于，通过多个启动过程，它们分别采用相同的逻辑状态，以及非易失性存储器（104） 具有关于预定数据存储单元（102a）存储的信息。 由此，电子密钥由预定数据存储单元（102a）的相应逻辑状态定义。
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公开(公告)号：US20100164778A1
公开(公告)日：2010-07-01
申请号：US12601086
申请日：2008-05-27
申请人： Simon M. Louwsma , Maarten Vertregt
发明人： Simon M. Louwsma , Maarten Vertregt
IPC分类号： H03M1/38
摘要： During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence.
摘要翻译： 在逐次近似模拟到数字转换期间，选择一系列连续的数字参考值，其朝向模拟输入信号的数字表示收敛。 根据连续的数字参考值产生模拟参考信号，并与模拟输入信号进行比较。 根据比较结果选择数字参考值。 在数字参考值的选择中，数字参考值之间的连续步骤分别根据多个先前递归周期的比较器结果的值来选择。 比较结果定义了一系列连续较窄的数字值范围，其中包含模拟输入信号的数字表示。 使用多个比较器结果来选择数字参考值中的步骤使得可以减小比较结果是否已经确定的不确定性。 这又可以减小连续范围的尺寸，这加快了收敛速度。
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6.发明申请Resistor network such as a resistor ladder network and a method for manufacturing such a resistor network 有权电阻网络如电阻梯形网络以及制造这种电阻网络的方法公开(公告)号：US20050224915A1
公开(公告)日：2005-10-13
申请号：US10517106
申请日：2003-05-21
申请人： Hans Tuinhout , Gian Hoogzaad , Maarten Vertregt
发明人： Hans Tuinhout , Gian Hoogzaad , Maarten Vertregt
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H03M1/06 , H01L29/00
CPC分类号： H01L27/0802
摘要： The invention relates to a resistor network (2) such as a resistor ladder network, comprising at least a resistor body (4) which is provided with at least a column (6) of taps (8) situated between a first tap and a second tap, wherein, in use, at least two taps can be connected with respective first and second sources of reference input potentials, and wherein each tap of the at least one column of taps can be used for outputting an output potential via a contact area which is connected with the concerning tap, wherein the resistor body (4) comprises a multiple of resistor sub-bodies (5), wherein each resistor sub-body (5) is connected with a column (6) of taps (8), and wherein the only electrical connections between the resistor sub-bodies (5) are established by electrical connections via taps (8) connected with the resistor sub-bodies (5). Furthermore the invention relates to a method for manufacturing a resistor network (2) such as a resistor ladder network.
摘要翻译： 本发明涉及一种电阻网络（2），例如电阻梯形网络，至少包括一个电阻体（4），该电阻器体（4）至少设置有位于第一抽头和第二抽头之间的抽头（6）的至少一列 抽头，其中在使用中，至少两个抽头可以与相应的第一和第二参考输入电位源连接，并且其中所述至少一列抽头的每个抽头可以用于经由接触区域输出输出电位，所述接触区域 与所述有关抽头连接，其中所述电阻体（4）包括多个电阻子体（5），其中每个电阻子体（5）与抽头（8）的列（6）连接，以及 其中通过与电阻子体（5）连接的抽头（8）的电连接来建立电阻子体（5）之间的唯一电连接。 此外，本发明涉及一种用于制造诸如电阻梯形网络的电阻网络（2）的方法。
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公开(公告)号：US5781176A
公开(公告)日：1998-07-14
申请号：US643069
申请日：1996-04-30
IPC分类号： G01R13/20 , G01R13/02 , G01R13/32 , G01R13/34 , G01R13/40 , G06T5/00 , G06T11/20 , G09G5/00 , G09G5/20 , G09G1/28
CPC分类号： G01R13/02 , G01R13/408
摘要： A structure with fine details, such as a periodic signal, is displayed on a raster display. To avoid aliasing due to an interference between the details and the columns and row pattern of the raster display each of the points representing the structure to be displayed is allocated to pixels in adjacent columns and/or rows. Allocation occurs by means of a stochastic procedure in which the probability to allocate a point to a pixel is dependent on the position of the point with respect to the pixel. Accumulated pixel-values are converted into a limited number of grey-values by means of an additional procedure that allows for fixed proportions of the pixels to have the same grey-value.
摘要翻译： 具有精细细节的结构（例如周期性信号）被显示在光栅显示器上。 为了避免由于细节和光栅显示的列和行图案之间的干扰而导致的混叠，将表示要显示的结构的每个点的每个点分配给相邻列和/或行中的像素。 通过随机过程进行分配，其中将点分配给像素的概率取决于点相对于像素的位置。 累积的像素值通过允许固定比例的像素具有相同灰度值的附加过程转换成有限数量的灰度值。
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公开(公告)号：US08690065B2
公开(公告)日：2014-04-08
申请号：US12673458
申请日：2008-08-12
IPC分类号： G06K19/06
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (μA, μB, μC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译： 本发明公开了一种用于安全地存储码字的集成电路（10）。 码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。 本发明还公开了一种读取器装置（15），一种用于从集成电路（10）确定码字的值的方法，以及用于改变码字值的方法。
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公开(公告)号：US20120127775A1
公开(公告)日：2012-05-24
申请号：US12673458
申请日：2008-08-12
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (μA, μB, μC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译： 本发明公开了一种用于安全地存储码字的集成电路（10）。 码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。 本发明还公开了一种读取器装置（15），一种用于从集成电路（10）确定码字的值的方法，以及用于改变码字值的方法。
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公开(公告)号：US08089302B2
公开(公告)日：2012-01-03
申请号：US12676914
申请日：2008-09-09
CPC分类号： H03K19/018528 , G11C27/026
摘要： The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages. The transistor element is configured such that in case a differential voltage between the first predefined alternating voltage and the second predefined alternating voltage is higher than the predefined threshold voltage and the first switching unit is not conductive the third terminal is charged with the first predefined alternating voltage.
摘要翻译： 本申请涉及一种包括具有至少三个端子的第一晶体管元件和至少一个开关单元的装置。 本申请还涉及一种其上存储有计算机程序的计算机可读介质和包括该装置的跟踪和保持电路的方法。 该装置包括具有至少三个端子的第一晶体管元件，其中第一端子被提供有第一电压，并且其中第二端子被提供有第二电压。 该装置包括第一开关单元，其中第三端子经由第一开关单元连接到地电位。 晶体管元件包括预定义的阈值电压。 第一电压和第二电压是预定的交流电压。 晶体管元件被配置为使得在第一预定交流电压和第二预定交流电压之间的差分电压高于预定阈值电压并且第一开关单元不导通的情况下，第三端子被充电第一预定交流电压 。
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