-
公开(公告)号：US08690065B2
公开(公告)日：2014-04-08
申请号：US12673458
申请日：2008-08-12
IPC分类号： G06K19/06
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (μA, μB, μC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译： 本发明公开了一种用于安全地存储码字的集成电路（10）。 码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。 本发明还公开了一种读取器装置（15），一种用于从集成电路（10）确定码字的值的方法，以及用于改变码字值的方法。
-
公开(公告)号：US20120127775A1
公开(公告)日：2012-05-24
申请号：US12673458
申请日：2008-08-12
摘要： The invention discloses an integrated circuit (10) for securely storing a codeword. The value of the codeword is dependent on the mobility (μA, μB, μC) of at least one transistor (TRA, TRB, TRC) of the integrated circuit. The invention further discloses a reader means (15), a method for determining the value of the codeword from the integrated circuit (10), and a method for altering the value of the codeword.
摘要翻译： 本发明公开了一种用于安全地存储码字的集成电路（10）。 码字的值取决于集成电路的至少一个晶体管（TRA，TRB，TRC）的迁移率（μA，μB，μC）。 本发明还公开了一种读取器装置（15），一种用于从集成电路（10）确定码字的值的方法，以及用于改变码字值的方法。
-
公开(公告)号：US07605740B2
公开(公告)日：2009-10-20
申请号：US12097040
申请日：2006-12-08
申请人： Marcel Pelgrom , Atul Katoch , Maarten Vertregt
发明人： Marcel Pelgrom , Atul Katoch , Maarten Vertregt
IPC分类号： H03M1/36
CPC分类号： H03M1/0673 , H03M1/365
摘要： A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.
摘要翻译： 闪存模数转换器包括由参考电压源供电的电阻串，用于提供一组等距参考电压，以及一组比较器，用于将模拟输入信号与参考电压进行比较。 一组开关被布置和控制以执行用于减轻组件之间的错配的影响的算法。 开关布置在参考电压源和电阻串之间，从而避免了比较器的参考输入中的开关。 电阻串优选为圆形。 转换器可以处理差分信号。
-
公开(公告)号：US08874394B2
公开(公告)日：2014-10-28
申请号：US13132550
申请日：2009-11-18
IPC分类号： G01R19/00 , G01R29/26 , G05D3/12 , G01R19/165 , G01R31/30
CPC分类号： G01R31/3004 , G01R19/16552 , G01R19/16571
摘要： Apparatus and method for IR-drop and supply noise measurements in electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.
摘要翻译： 电子电路中红外降噪和噪声测量的装置和方法。 电路中的感兴趣点处的第一电压被采样并在电路的静态模式下被存储。随后，电路进入操作模式，并且将第二电压采样并保持在 同样的兴趣点。 比较第一和第二电压，并将相应的电压信号传递到系统输出。
-
公开(公告)号：US20110140730A1
公开(公告)日：2011-06-16
申请号：US12995445
申请日：2009-05-14
申请人： Victor Zieren , Harold Geradus Pieter Hendrikus Benten , Agnese Antonietta Maria Bargagli-Stoffi , Marcel Pelgrom , Hendricus Joseph Maria Veendrick
发明人： Victor Zieren , Harold Geradus Pieter Hendrikus Benten , Agnese Antonietta Maria Bargagli-Stoffi , Marcel Pelgrom , Hendricus Joseph Maria Veendrick
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/048 , H01L22/34 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05551 , H01L2224/05554 , H01L2224/05578 , H01L2224/05599 , H01L2224/13 , H01L2224/13028 , H01L2224/13099 , H01L2224/1613 , H01L2224/859 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01051 , H01L2924/01057 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/00
摘要： The present invention relates to a detection circuitry for detecting bonding conditions on segmented bond pads of a semiconductor device, the bonding conditions representing good or bad contacts on the bond pads. The detection circuitry comprises a segmented bond pad (1, 11) having at least two parts (2, 3, 12, 13) being electrically separated from each other, and a supplying unit (S1, S2, R1, R2) being adapted for supplying predetermined signals to at least one of the at least two parts of the segmented bond pad. Furthermore, a detector (4, 14) is provided for receiving from at least one of the at least two parts of the segmented bond pad sensing signals derived from said predetermined signals, and for determining the bonding conditions based on said received sensing signals indicative of a good or bad bonding contact on the segmented bond pad.
摘要翻译： 本发明涉及一种用于检测半导体器件的分段接合焊盘上的接合条件的检测电路，所述接合条件表示接合焊盘上的良好或不良接触。 所述检测电路包括具有彼此电分离的至少两个部分（2,3,13,13）的分段接合焊盘（1,11），以及供应单元（S1，S2，R1，R2），适于 向分段接合焊盘的至少两个部分中的至少一个提供预定信号。 此外，提供检测器（4,14），用于从分段焊接感测信号的至少两个部分中的至少一个接收从所述预定信号导出的感测信号，并且用于基于所述接收的感测信号来确定指示 在分段接合垫上的良好或不良的接合接触。
-
公开(公告)号：US20080007246A1
公开(公告)日：2008-01-10
申请号：US11720190
申请日：2005-11-07
IPC分类号： G01R31/26
CPC分类号： G01R31/31723 , G01R31/317
摘要： An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).
摘要翻译： 集成电路包括多个检测电路（12），每个检测电路用于检测相应的物理操作参数是否高于或低于相应的参考值。 集成电路包含用于将表示来自逐次逼近更新电路（14）的各个参考值的数字数据信号移位到感测电路（12）并返回到逐次逼近更新电路（14）的串行移位寄存器（11）。 感测电路（12）的检测结果用数字数据信号转移到逐次逼近更新电路（14）。 逐次逼近更新电路（14）用于形成数字数据，使得参考值在模数转换过程期间形成物理操作参数值的逐次逼近。 以这种方式，逐次逼近更新电路（14）由多个感测电路（12）共享。
-
7.发明申请Semiconductor device with test structure and semiconductor device test method 审中-公开具有测试结构和半导体器件测试方法的半导体器件公开(公告)号：US20100315114A1
公开(公告)日：2010-12-16
申请号：US12317138
申请日：2009-06-22
CPC分类号： G01R31/2884 , G01R31/3161
摘要： The invention relates to a semiconductor device comprising a test structure (100) for detecting variations in the structure of the semiconductor device, the test structure (100) comprising a first supply rail (110), a second supply rail (120), a ring oscillator (130) coupled between the first supply rail (110) and second supply rail (120), the ring oscillator (130) having an output (132) for providing a test result signal, and an array (140) of individually controllable transistors (142) coupled in parallel between the first supply rail (110) and the ring oscillator (130). Variations in the current output of the respective transistors (142) in the array (140) lead to variations in the respective output frequencies of the ring oscillator (130). This gives a qualitative indication of the aforementioned structural variations. More accurate results can be obtained by inclusion of a reference current source (160) for calibrating the ring oscillator (130) prior to the measurement of the current output of the individual transistors (142).
摘要翻译： 本发明涉及一种包括用于检测半导体器件结构变化的测试结构（100）的半导体器件，该测试结构（100）包括第一电源轨（110），第二电源轨（120），环 耦合在第一电源轨道（110）和第二电源轨道（120）之间的振荡器（130），环形振荡器（130）具有用于提供测试结果信号的输出（132）和独立可控晶体管的阵列（140） （142），并联在所述第一电源轨（110）和所述环形振荡器（130）之间。 阵列（140）中的相应晶体管（142）的电流输出的变化导致环形振荡器（130）的相应输出频率的变化。 这给出了上述结构变化的定性指示。 通过在测量各个晶体管（142）的电流输出之前，包括用于校准环形振荡器（130）的参考电流源（160）可以获得更准确的结果。
-
公开(公告)号：US20080143348A1
公开(公告)日：2008-06-19
申请号：US11722629
申请日：2005-12-19
IPC分类号： G01R27/26
CPC分类号： G01R31/2853 , G01R27/2605
摘要： The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit (10) is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.
摘要翻译： 本发明涉及一种用于硅互连电容（Cx）提取的片上电路，其被自适应于集成晶体管中的工艺变化。 电路（10）包括信号产生装置（20），用于产生连接到第一和第二信号延迟装置（31,32）的周期性脉冲信号，用于各自延迟所述脉冲信号，其中所述第二信号延迟装置（32）被配置 具有由所述互连电容（Cx）影响的延迟; 用于连接所述各个第一和第二延迟装置（31,32）的相应第一和所述第二延迟信号的逻辑异或门（35），所述逻辑异或门（35）连接到信号积分装置（40）; 并且所述信号积分装置（40）连接到模数转换装置（50）。 虽然传统的无补偿系统中的误差，如延迟线，误差可以高达30％，但在根据本发明的电路中，由于前端处理变化引起的误差约为2％。 此外，以数字格式提供输出，因此可以用简单的外部硬件快速测量。 此外，脉冲信号频率可以用作监视器来测量前端的过程变化。 此外，由于电路（10）非常准确且非常容易测量，因此作为未来制造的每个芯片的过程监视器是最佳选择。
-
9.发明申请公开(公告)号：US20110246110A1
公开(公告)日：2011-10-06
申请号：US13132550
申请日：2009-11-18
CPC分类号： G01R31/3004 , G01R19/16552 , G01R19/16571
摘要： Apparatus and method for IR-drop and supply noise measurements electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.
摘要翻译： 用于红外降噪和噪声测量的电子电路的装置和方法。 电路中的感兴趣点处的第一电压被采样并在电路的静态模式下被存储。随后，电路进入操作模式，并且将第二电压采样并保持在 同样的兴趣点。 比较第一和第二电压，并将相应的电压信号传递到系统输出。
-
公开(公告)号：US07928882B2
公开(公告)日：2011-04-19
申请号：US11720190
申请日：2005-11-07
CPC分类号： G01R31/31723 , G01R31/317
摘要： An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).
摘要翻译： 集成电路包括多个检测电路（12），每个检测电路用于检测相应的物理操作参数是否高于或低于相应的参考值。 集成电路包含用于将表示来自逐次逼近更新电路（14）的各个参考值的数字数据信号移位到感测电路（12）并返回到逐次逼近更新电路（14）的串行移位寄存器（11）。 感测电路（12）的检测结果用数字数据信号转移到逐次逼近更新电路（14）。 逐次逼近更新电路（14）用于形成数字数据，使得参考值在模数转换过程期间形成物理操作参数值的逐次逼近。 以这种方式，逐次逼近更新电路（14）由多个感测电路（12）共享。
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.018 秒)
