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公开(公告)号：US20240313089A1
公开(公告)日：2024-09-19
申请号：US18422787
申请日：2024-01-25
发明人： Ryo TANAKA , Katsunori UENO , Shinya TAKASHIMA
IPC分类号： H01L29/66 , H01L21/225 , H01L21/265 , H01L21/266 , H01L29/08 , H01L29/20 , H01L29/78
CPC分类号： H01L29/66522 , H01L21/2258 , H01L21/26546 , H01L21/266 , H01L29/086 , H01L29/2003 , H01L29/66712 , H01L29/7802
摘要： The nitride semiconductor device includes a field effect transistor formed in a gallium nitride layer. The field effect transistor includes: a gate insulator film formed on a side of a first principal face of the gallium nitride layer; a p type region being in contact with the gate insulator film; an n type region being in contact with the p type region in a direction parallel to an interface between the p type region and the gate insulator film; a first electrode being in contact with the n type region. The p type region includes a first region that is in contact with the gate insulator film and a second region that is in contact with the gate insulator film and lies in the first direction between the first region and the n type region. The second region has a higher concentration of p type impurities than the first region.
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公开(公告)号：US20210043737A1
公开(公告)日：2021-02-11
申请号：US16919560
申请日：2020-07-02
发明人： Shinya TAKASHIMA , Ryo TANAKA , Katsunori UENO
IPC分类号： H01L29/20 , H01L21/02 , H01L21/225 , H01L21/324
摘要： A method for manufacturing a nitride semiconductor device includes: selectively ion-implanting an element that is other than p-type impurities and n-type impurities into a first region in a first primary surface of a gallium nitride layer so as to generate crystal defects in the first region; selectively ion-implanting a p-type impurity into a second region in the gallium nitride layer, the second region being shallower than the first region in a depth direction and being within the first region in a plan view; and thermally treating said gallium nitride layer that has been ion-implanted with said element and said p-type impurity so as to thermally diffuse said p-type impurity in the second region into a third region that is within the first region and that surrounds a bottom and sides of the second region.
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公开(公告)号：US20180005843A1
公开(公告)日：2018-01-04
申请号：US15609035
申请日：2017-05-31
发明人： Shinya TAKASHIMA , Katsunori UENO , Masaharu EDO , Akira UEDONO
IPC分类号： H01L21/324 , H01L21/265 , H01L29/20 , H01L29/66
CPC分类号： H01L21/3245 , H01L21/26546 , H01L29/2003 , H01L29/66204 , H01L29/66522 , H01L29/7802 , H01L29/8611
摘要： An ion implantation results in defects generated in a nitride semiconductor layer. If the nitride semiconductor layer is set at a particular temperature for a predetermined time period after the ion implantation, the defects may probably be clustering. Provided is a manufacturing method of a semiconductor device including a nitride semiconductor layer comprising: implanting impurities in the nitride semiconductor layer; and increasing a temperature of the nitride semiconductor layer from an initial temperature to a target temperature and annealing the nitride semiconductor layer at the target temperature for a predetermined time period; wherein in the annealing, in at least part of temperature regions below a first temperature between the initial temperature and the target temperature, the nitride semiconductor layer is annealed at a temperature increase speed lower than in a temperature region not lower than the first temperature.
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4.发明申请METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR DEVICE 审中-公开制造氮化物半导体器件和氮化物半导体器件的方法公开(公告)号：US20160365438A1
公开(公告)日：2016-12-15
申请号：US15060597
申请日：2016-03-03
发明人： Shinya TAKASHIMA , Ryo TANAKA , Katsunori UENO , Masaharu EDO
IPC分类号： H01L29/78 , H01L21/306 , H01L29/66 , H01L29/207 , H01L29/10 , H01L21/324 , H01L29/20
CPC分类号： H01L29/7802 , H01L21/3245 , H01L29/1095 , H01L29/2003 , H01L29/66522 , H01L29/66712
摘要： The region having the surface roughness has nitrogen vacancies, which serve as compensating donors for acceptors and therefore cannot achieve a sufficiently high p-type carrier concentration. In addition, the surface of the GaN-based material may be contaminated as a result of diffusion of impurities from the protective film or insufficient removal of the protective film. Such contamination may adversely affect the subsequent steps or the characteristics of completed devices.A first aspect of the innovations herein provides a method of manufacturing a nitride semiconductor device, including thermally treating a nitride semiconductor layer or removing a film formed on a front surface of the nitride semiconductor layer, and polishing the front surface of the nitride semiconductor layer after the thermally treating or the removing.
摘要翻译： 本发明的第一方面提供了一种制造氮化物半导体器件的方法，包括热处理氮化物半导体层或去除形成在氮化物半导体层的前表面上的膜，以及在氮化物半导体层的前表面之后研磨氮化物半导体层的前表面 热处理或去除。
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公开(公告)号：US20230387292A1
公开(公告)日：2023-11-30
申请号：US18180353
申请日：2023-03-08
发明人： Tsurugi KONDO , Katsunori UENO , Shinya TAKASHIMA , Ryo TANAKA
CPC分类号： H01L29/7813 , H01L29/2003 , H01L29/1095
摘要： A nitride semiconductor device including: a gallium nitride substrate; and a vertical MOSFET provided on the gallium nitride substrate, the vertical MOSFET including:
an N-type drift region provided in the gallium nitride substrate; a P-type well region provided in the drift region; an N-type source region provided in the well region; a gate insulating film provided on a surface of the well region; and a gate electrode provided on the surface of the well region via the gate insulating film, wherein the well region includes a first well region and a second well region higher in acceptor element concentration than the first well region, the second well region being located between the first well region and the gate insulating film and being in contact with the source region.-
公开(公告)号：US20190115215A1
公开(公告)日：2019-04-18
申请号：US15936436
申请日：2018-03-27
发明人： Shinya TAKASHIMA , Katsunori UENO , Masaharu EDO
IPC分类号： H01L21/225 , H01L29/207 , H01L29/20 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/10 , H01L21/266 , H01L21/265
CPC分类号： H01L21/2258 , H01L21/26553 , H01L21/266 , H01L29/086 , H01L29/1095 , H01L29/2003 , H01L29/207 , H01L29/66522 , H01L29/66712 , H01L29/7802
摘要： A vertical semiconductor apparatus includes: a gallium nitride substrate; a gallium nitride semiconductor layer on the gallium nitride substrate; a p-type impurity region in the gallium nitride semiconductor layer and having an element to function as an acceptor for gallium nitride; an n-type impurity region in the p-type impurity region and having an element to function as a donor for gallium nitride; and an electrode provided contacting a rear surface of the gallium nitride substrate. The element to function as the donor in the n-type impurity region includes: a first impurity element to enter sites of gallium atoms in the gallium nitride semiconductor layer; and a second impurity element different from the first impurity element and to enter sites of nitrogen atoms in the gallium nitride semiconductor layer. In the n-type impurity region, a concentration of the first impurity element is higher than that of the second impurity element.
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公开(公告)号：US20150380238A1
公开(公告)日：2015-12-31
申请号：US14848214
申请日：2015-09-08
发明人： Shinya TAKASHIMA , Ryo TANAKA , Katsunori UENO , Masaharu EDO
IPC分类号： H01L21/02 , H01L29/20 , H01L21/324
CPC分类号： H01L21/0254 , C23C16/303 , C23C16/56 , C30B23/02 , C30B25/02 , C30B29/406 , H01L21/02609 , H01L21/0262 , H01L21/18 , H01L21/22 , H01L21/3245 , H01L29/2003 , H01L29/66522 , H01L29/66712 , H01L29/7802 , H01L29/7827
摘要： A method for producing a semiconductor device having a nitride-based semiconductor layer includes forming an aluminum nitride layer on a surface of the nitride-based semiconductor layer at a forming temperature and in a growth atmosphere for aluminum nitride; and performing a thermal treatment on the nitride-based semiconductor layer and the aluminum nitride layer, at a treatment temperature that is higher than the forming temperature and in the growth atmosphere for aluminum nitride. For example, an n-GaN layer is formed on an n-GaN substrate, and thereafter the n-GaN layer is doped with an impurity. A cap layer of an epitaxial film made up of AlN is formed, by MOCVD, on the surface of the n-GaN layer. Thermal treatment for activation annealing activates the impurity in the n-GaN layer in an atmosphere that causes AlN to grow, or in an atmosphere in which growth and decomposition of AlN are substantially balanced.
摘要翻译： 一种具有氮化物系半导体层的半导体装置的制造方法，包括：在氮化物系半导体层的表面，在氮化铝的成膜温度和生长气氛下形成氮化铝层; 并且对于氮化铝基半导体层和氮化铝层，在高于成形温度的处理温度和氮化铝的生长气氛中进行热处理。 例如，在n-GaN衬底上形成n-GaN层，此后，n-GaN层掺杂有杂质。 通过MOCVD在n-GaN层的表面上形成由AlN构成的外延膜的盖层。 用于活化退火的热处理在使AlN生长的气氛中或在AlN的生长和分解基本平衡的气氛中激活n-GaN层中的杂质。
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公开(公告)号：US20240030322A1
公开(公告)日：2024-01-25
申请号：US18337032
申请日：2023-06-18
IPC分类号： H01L29/739 , H01L29/66 , H01L21/265 , H01L29/36
CPC分类号： H01L29/7397 , H01L29/66348 , H01L21/265 , H01L29/36
摘要： A manufacturing method of a semiconductor apparatus including: setting, depending on a distribution of the carrier concentrations that the buffer region should have, a dose amount of hydrogen ions to be implanted into a plurality of depth positions corresponding to the plurality of concentration peaks; and implanting, depending on the dose amount that is set in the setting, the hydrogen ions into the semiconductor substrate is provided. In the setting, among the plurality of concentration peaks, the dose amount of the hydrogen ions for a deepest peak farthest from the lower surface of the semiconductor substrate is set depending on a carbon concentration of the semiconductor substrate, and the dose amount for at least one of the concentration peaks other than the deepest peak is set regardless of the carbon concentration of the semiconductor substrate.
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公开(公告)号：US20180097063A1
公开(公告)日：2018-04-05
申请号：US15719607
申请日：2017-09-29
CPC分类号： H01L29/1095 , H01L21/0254 , H01L21/26546 , H01L29/0856 , H01L29/0873 , H01L29/2003 , H01L29/66446 , H01L29/66734 , H01L29/7813
摘要： In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.
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公开(公告)号：US20180012964A1
公开(公告)日：2018-01-11
申请号：US15607692
申请日：2017-05-30
发明人： Katsunori UENO , Shinya TAKASHIMA
IPC分类号： H01L29/207 , H01L29/423 , H01L29/20 , H01L29/78 , H01L29/66
CPC分类号： H01L29/207 , H01L29/2003 , H01L29/42356 , H01L29/66522 , H01L29/66666 , H01L29/7827
摘要： Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.
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