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1.发明申请PERFORMANCE MEASUREMENT OF DEVICE DEDICATED TO PHASE LOCKED LOOP USING SECOND ORDER SYSTEM APPROXIMATION 失效使用第二次订单系统逼近的相位锁定环路设备的性能测量公开(公告)号：US20060186871A1
公开(公告)日：2006-08-24
申请号：US10906412
申请日：2005-02-18
申请人： Faraydon Pakbaz , Stephen Wyatt
发明人： Faraydon Pakbaz , Stephen Wyatt
IPC分类号： G01R23/12
CPC分类号： G06F17/5036
摘要： A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.
摘要翻译： 用于测量专用于锁相环（PLL）的设备的性能的方法，系统和程序产品。 产生电阻 - 电感 - 电容（RLC）模型来模拟PLL。 将RLC模型和要测量的设备映射到测试电路中，并分析测试电路的特性，以确定如果连接到由RLC模型表示的PLL的设备是否能够满足所需的性能标准。 本发明可用于测量各种类型PLL的各种器件的性能。
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2.发明授权Circuit and method for asynchronous pipeline processing with variable request signal delay 有权具有可变请求信号延迟的异步流水线处理的电路和方法公开(公告)号：US08188765B2
公开(公告)日：2012-05-29
申请号：US12882425
申请日：2010-09-15
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F5/10 , G06F2205/104
摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.
摘要翻译： 公开了异步管线电路的实施例。 在电路的每个阶段，可变延迟线被并入到请求信号路径中。 抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。 基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟 信号沿请求信号路径传输。 使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。 还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。
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3.发明申请METHOD FOR SIMULTANEOUS CIRCUIT BOARD AND INTEGRATED CIRCUIT SWITCHING NOISE ANALYSIS AND MITIGATION 审中-公开同步电路板和集成电路开关噪声分析与减速方法公开(公告)号：US20090112558A1
公开(公告)日：2009-04-30
申请号：US11930436
申请日：2007-10-31
申请人： Umberto Garofano , Faraydon Pakbaz
发明人： Umberto Garofano , Faraydon Pakbaz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/40 , H05K1/0231 , H05K3/0005 , H05K2201/10689
摘要： A method and a design structure. The method includes: generating a board model of a circuit board design; generating a impedance spectrum of the board model; generating a chip model of an integrated circuit chip design; performing a transient analysis of the chip model using an ideal board power supply to generate an initial chip noise signature; based on the transient analysis, adding noise generators to the board model to generate a modified board model and to generate a latest board power supply; performing an additional transient analysis of the chip model using the modified board model and the latest board power supply to generate a latest noise signature; determining if the latest noise signature is within a predetermined chip noise specification; and if the latest noise signature is not within the predetermined chip noise specification, adding at least one decoupling capacitor to the modified board model.
摘要翻译： 一种方法和设计结构。 该方法包括：生成电路板设计的电路板模型; 产生板模型的阻抗谱; 生成集成电路芯片设计的芯片模型; 使用理想的电路板电源对芯片模型进行瞬态分析以产生初始的芯片噪声特征; 基于瞬态分析，向板模型添加噪声发生器，生成修改后的电路板模型，生成最新的电路板电源; 使用修改的电路板模型和最新的电路板电源对芯片模型进行额外的瞬态分析，以生成最新的噪声特征; 确定最新的噪声签名是否在预定的芯片噪声规范内; 并且如果最新的噪声特征不在预定的芯片噪声规范内，则将至少一个解耦电容器添加到修改的板模型。
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公开(公告)号：US08648634B2
公开(公告)日：2014-02-11
申请号：US13468268
申请日：2012-05-10
申请人： Ram Kelkar , Faraydon Pakbaz
发明人： Ram Kelkar , Faraydon Pakbaz
IPC分类号： H03L7/06
摘要： An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone.
摘要翻译： 提供了一种用于锁相环的输入抖动滤波器和使用方法。 该方法包括在反馈信号的下降沿周围产生掩蔽区域。 该方法还包括确定相位检测器的一个或多个输出落在屏蔽区内。 该方法还包括当相位检测器的一个或多个输出落在屏蔽区域内时忽略输入时钟噪声。
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5.发明授权Asynchronous circuit with an at-speed built-in self-test (BIST) architecture 有权具有高速内置自检（BIST）架构的异步电路公开(公告)号：US08612815B2
公开(公告)日：2013-12-17
申请号：US13327847
申请日：2011-12-16
IPC分类号： G01R31/28
CPC分类号： G01R31/31813 , G01R31/3187
摘要： Disclosed are integrated circuits that incorporate an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. Specifically, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal.
摘要翻译： 公开了集成电路，其包括具有内置自检（BIST）架构的异步电路，其使用用于高速测试的握手协议来检测卡住的故障。 具体来说，测试模式发生器将测试模式应用于异步电路，分析仪分析输出测试数据。 握手协议通过使用单个脉冲发生器来实现，该单个脉冲发生器向测试模式发生器施加单个脉冲以强制测试模式请求信号的切换，从而控制测试模式对异步电路的应用和随后的切换 的测试模式确认信号。 可以通过切换测试模式确认信号来强制产生该单个脉冲。
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6.发明授权Integrated circuit chip incorporating embedded thermal radiators for localized, on-demand, heating and a system and method for designing such an integrated circuit chip 失效集成电路芯片包含用于局部，点播，加热的嵌入式散热器，以及用于设计这种集成电路芯片的系统和方法公开(公告)号：US08756549B2
公开(公告)日：2014-06-17
申请号：US12984638
申请日：2011-01-05
CPC分类号： H05B1/0227 , G05D23/1934
摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
摘要翻译： 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。
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7.发明申请CIRCUIT AND METHOD FOR ASYNCHRONOUS PIPELINE PROCESSING WITH VARIABLE REQUEST SIGNAL DELAY 有权具有可变请求信号延迟的异步管道加工的电路和方法公开(公告)号：US20120062300A1
公开(公告)日：2012-03-15
申请号：US12882425
申请日：2010-09-15
IPC分类号： H03H11/26
CPC分类号： G06F5/10 , G06F2205/104
摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.
摘要翻译： 公开了异步管线电路的实施例。 在电路的每个阶段，可变延迟线被并入到请求信号路径中。 抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。 基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟 信号沿请求信号路径传输。 使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。 还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。
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8.发明申请公开(公告)号：US20060190229A1
公开(公告)日：2006-08-24
申请号：US10906509
申请日：2005-02-23
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5036
摘要： A method (1100) of creating a behavioral model of a portion (400) of an electrical circuit. The method includes collecting data by measuring an S-parameter of the circuit portion. A transfer function approximation (412, 1000) is then constructed from the S-parameter data. The transfer function approximation is simplified to provide a partial fraction expansion (416). The behavioral model includes a passive filter (420, 1004) designed to represent the partial fraction expansion.
摘要翻译： 一种创建电路部分（400）的行为模型的方法（1100）。 该方法包括通过测量电路部分的S参数来收集数据。 然后从S参数数据构建传递函数近似（412,1000）。 传递函数近似被简化以提供部分分数扩展（416）。 行为模型包括被设计为表示部分分数膨胀的无源过滤器（420,1004）。
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9.发明授权Performance measurement of device dedicated to phase locked loop using second order system approximation 失效使用二阶系统逼近的专用于锁相环的设备的性能测量公开(公告)号：US07084615B1
公开(公告)日：2006-08-01
申请号：US10906412
申请日：2005-02-18
申请人： Faraydon Pakbaz , Stephen D. Wyatt
发明人： Faraydon Pakbaz , Stephen D. Wyatt
CPC分类号： G06F17/5036
摘要： A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.
摘要翻译： 用于测量专用于锁相环（PLL）的设备的性能的方法，系统和程序产品。 产生电阻 - 电感 - 电容（RLC）模型来模拟PLL。 将RLC模型和要测量的设备映射到测试电路中，并分析测试电路的特性，以确定如果连接到由RLC模型表示的PLL的设备是否能够满足所需的性能标准。 本发明可用于测量各种类型PLL的各种器件的性能。
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10.发明申请ASYNCHRONOUS CIRCUIT WITH AN AT-SPEED BUILT-IN SELF-TEST (BIST) ARCHITECTURE 有权具有快速内置自检（BIST）架构的异步电路公开(公告)号：US20130159803A1
公开(公告)日：2013-06-20
申请号：US13327847
申请日：2011-12-16
IPC分类号： G01R31/28
CPC分类号： G01R31/31813 , G01R31/3187
摘要： Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults.
摘要翻译： 公开了集成电路的实施例，该集成电路结合具有内置自检（BIST）架构的异步电路，使用用于高速测试的握手协议来检测卡住故障。 在实施例中，测试模式发生器将测试模式应用于异步电路，分析器分析输出测试数据。 握手协议通过使用单个脉冲发生器来实现，该单个脉冲发生器向测试模式发生器施加单个脉冲以强制测试模式请求信号的切换，从而控制测试模式对异步电路的应用和随后的切换 的测试模式确认信号。 可以通过切换测试模式确认信号来强制产生该单个脉冲。 可选地，可以将时间约束添加到捕获输出测试数据以允许检测延迟故障。
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