公开(公告)号：US20060081926A1

公开(公告)日：2006-04-20

申请号：US11259489

申请日：2005-10-25

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

公开(公告)号：US5897363A

公开(公告)日：1999-04-27

申请号：US982809

申请日：1997-12-02

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/7833 ,  H01L29/7836 ,  H01L29/66575 ,  Y10S257/90

摘要： Disclosed is a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. An anneal step follows. The result is a shallow junction with a variable concentration profile gradation of dopant. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage.

摘要翻译： 公开了一种用于形成具有可变浓度分布层级的掺杂剂的浅结的方法。 本发明的方法包括：首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 退火步骤如下。 结果是具有掺杂剂的可变浓度分布灰度的浅结。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。

公开(公告)号：US07179703B2

公开(公告)日：2007-02-20

申请号：US11259489

申请日：2005-10-25

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

摘要翻译： 公开了用于形成具有可变浓度分布层级的掺杂剂的浅结的方法。 本发明的方法包括首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 在各种实施例中，可以以相反的顺序执行掺杂步骤。 此外，可以在任何掺杂操作之后执行退火步骤。

公开(公告)号：US06717211B2

公开(公告)日：2004-04-06

申请号：US09981549

申请日：2001-10-17

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： An electrical device including a shallow junction with a variable concentration profile gradation of dopants. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage. The electrical device includes a semiconductor substrate having a top surface, a gate region overlapping a portion of the semiconductor substrate, and a source/drain region disposed within the semiconductor substrate. The source/drain region includes an inner portion and an outer portion, wherein the inner portion extends from the top surface of the semiconductor substrate to a bottom periphery and does not underlap the gate region, and the outer portion extends from the bottom periphery of the inner portion and underlaps the gate region. An electrical insulation layer is situated upon the gate region and overlaps the source/drain region.

摘要翻译： 包括具有可变浓度分布层级的掺杂剂的浅结的电气装置。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。 电气装置包括具有顶表面，与半导体衬底的一部分重叠的栅极区域和设置在半导体衬底内的源极/漏极区域的半导体衬底。 源极/漏极区域包括内部部分和外部部分，其中内部部分从半导体衬底的顶表面延伸到底部周边，并且不会使栅极区域下凹，并且外部部分从底部周边延伸 内部部分并且使栅极区域重叠。 电绝缘层位于栅极区上并与源极/漏极区重叠。

公开(公告)号：US07060599B2

公开(公告)日：2006-06-13

申请号：US10804578

申请日：2004-03-19

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L21/425 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

摘要翻译： 公开了具有用于形成具有可变浓度分布层级的掺杂剂的浅结的方法和电子器件。 本发明的方法包括首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 在各种实施例中，可以以相反的顺序执行掺杂步骤。 此外，可以在任何掺杂操作之后执行退火步骤。

公开(公告)号：US06359310B1

公开(公告)日：2002-03-19

申请号：US09196515

申请日：1998-11-20

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed is an electrical device including a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. An anneal step follows. The result is a shallow junction with a variable concentration profile gradation of dopant. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage.

摘要翻译： 公开了一种电气装置，其包括用于形成具有可变浓度分布等级的掺杂剂的浅结的方法。 本发明的方法包括：首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 退火步骤如下。 结果是具有掺杂剂的可变浓度分布灰度的浅结。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。

公开(公告)号：US08451650B2

公开(公告)日：2013-05-28

申请号：US13524809

申请日：2012-06-15

申请人： Fernando Gonzalez ,  Chandra V. Mouli

发明人： Fernando Gonzalez ,  Chandra V. Mouli

IPC分类号： G11C11/24

CPC分类号： G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US08374037B2

公开(公告)日：2013-02-12

申请号：US13186796

申请日：2011-07-20

申请人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

发明人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

IPC分类号： G11C16/10

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C16/0483 ,  H01L27/11521

摘要： A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

摘要翻译： 半导体磁存储器件具有形成在存储单元上的磁性隧道结。 存储单元具有由浮动栅极包围的控制门。 浮动栅极通过钉扎层耦合到磁性隧道结，该钉扎层保持结的下部磁性层的磁性取向。 耦合到控制栅极的选定字线的电流产生第一磁场。 通过单元选择线的电流产生与第一磁场正交的第二磁场。 这改变了结的上部磁性层的磁性取向以降低其电阻，从而允许编程/擦除线上的写入/擦除电压对浮动栅极进行编程/擦除。

公开(公告)号：US20120258577A1

公开(公告)日：2012-10-11

申请号：US13524809

申请日：2012-06-15

申请人： Fernando Gonzalez ,  Chandra V. Mouli

发明人： Fernando Gonzalez ,  Chandra V. Mouli

IPC分类号： H01L21/8239

CPC分类号： G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US20110080783A1

公开(公告)日：2011-04-07

申请号：US12966430

申请日：2010-12-13

申请人： Parag Banerjee ,  Terry Grafron ,  Fernando Gonzalez

发明人： Parag Banerjee ,  Terry Grafron ,  Fernando Gonzalez

IPC分类号： G11C11/15

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C16/0483 ,  H01L27/11521

摘要： A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

摘要翻译： 半导体磁存储器件具有在存储单元上形成的磁隧道结。 存储单元具有由浮动栅极包围的控制栅极。 浮动栅极通过钉扎层耦合到磁性隧道结，该钉扎层保持结的下部磁性层的磁性取向。 耦合到控制栅极的选定字线的电流产生第一磁场。 通过单元选择线的电流产生与第一磁场正交的第二磁场。 这改变了结的上部磁性层的磁性取向以降低其电阻，从而允许编程/擦除线上的写入/擦除电压对浮动栅极进行编程/擦除。