公开(公告)号：US20060081926A1

公开(公告)日：2006-04-20

申请号：US11259489

申请日：2005-10-25

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

公开(公告)号：US5897363A

公开(公告)日：1999-04-27

申请号：US982809

申请日：1997-12-02

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/7833 ,  H01L29/7836 ,  H01L29/66575 ,  Y10S257/90

摘要： Disclosed is a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. An anneal step follows. The result is a shallow junction with a variable concentration profile gradation of dopant. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage.

摘要翻译： 公开了一种用于形成具有可变浓度分布层级的掺杂剂的浅结的方法。 本发明的方法包括：首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 退火步骤如下。 结果是具有掺杂剂的可变浓度分布灰度的浅结。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。

公开(公告)号：US07179703B2

公开(公告)日：2007-02-20

申请号：US11259489

申请日：2005-10-25

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

摘要翻译： 公开了用于形成具有可变浓度分布层级的掺杂剂的浅结的方法。 本发明的方法包括首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 在各种实施例中，可以以相反的顺序执行掺杂步骤。 此外，可以在任何掺杂操作之后执行退火步骤。

公开(公告)号：US06717211B2

公开(公告)日：2004-04-06

申请号：US09981549

申请日：2001-10-17

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： An electrical device including a shallow junction with a variable concentration profile gradation of dopants. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage. The electrical device includes a semiconductor substrate having a top surface, a gate region overlapping a portion of the semiconductor substrate, and a source/drain region disposed within the semiconductor substrate. The source/drain region includes an inner portion and an outer portion, wherein the inner portion extends from the top surface of the semiconductor substrate to a bottom periphery and does not underlap the gate region, and the outer portion extends from the bottom periphery of the inner portion and underlaps the gate region. An electrical insulation layer is situated upon the gate region and overlaps the source/drain region.

摘要翻译： 包括具有可变浓度分布层级的掺杂剂的浅结的电气装置。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。 电气装置包括具有顶表面，与半导体衬底的一部分重叠的栅极区域和设置在半导体衬底内的源极/漏极区域的半导体衬底。 源极/漏极区域包括内部部分和外部部分，其中内部部分从半导体衬底的顶表面延伸到底部周边，并且不会使栅极区域下凹，并且外部部分从底部周边延伸 内部部分并且使栅极区域重叠。 电绝缘层位于栅极区上并与源极/漏极区重叠。

公开(公告)号：US07060599B2

公开(公告)日：2006-06-13

申请号：US10804578

申请日：2004-03-19

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L21/425 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

摘要翻译： 公开了具有用于形成具有可变浓度分布层级的掺杂剂的浅结的方法和电子器件。 本发明的方法包括首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 在各种实施例中，可以以相反的顺序执行掺杂步骤。 此外，可以在任何掺杂操作之后执行退火步骤。

公开(公告)号：US06359310B1

公开(公告)日：2002-03-19

申请号：US09196515

申请日：1998-11-20

申请人： Fernando Gonzalez ,  Randhir Thakur

发明人： Fernando Gonzalez ,  Randhir Thakur

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S257/90

摘要： Disclosed is an electrical device including a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. An anneal step follows. The result is a shallow junction with a variable concentration profile gradation of dopant. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage.

摘要翻译： 公开了一种电气装置，其包括用于形成具有可变浓度分布等级的掺杂剂的浅结的方法。 本发明的方法包括：首先提供和掩蔽要在其上形成浅结的过程中集成电路晶片上的表面。 接下来，进行低离子速度和低能离子轰击等离子体掺杂或PLAD操作以提供浅结的高掺杂内部部分。 在另一步骤中，使用中功率注入机进行较高的离子速度和能量常规的离子轰击注入掺杂操作，以用轻掺杂的外部部分延伸浅结边界。 退火步骤如下。 结果是具有掺杂剂的可变浓度分布灰度的浅结。 该结适用于在MOS晶体管中形成源极和漏极区域，特别是在接触或互连用于接合源极和漏极区域的情况下。 掺杂剂的可变浓度分布层次有助于保持适当的阈值电压电平并减少反向偏置电流泄漏。

公开(公告)号：US07579232B1

公开(公告)日：2009-08-25

申请号：US12216924

申请日：2008-07-11

申请人： Er-Xuan Ping ,  Randhir Thakur ,  Klaus Scheugraf

发明人： Er-Xuan Ping ,  Randhir Thakur ,  Klaus Scheugraf

IPC分类号： H01L21/8234 ,  H01L21/8222 ,  H01L21/425

CPC分类号： H01L27/1021 ,  H01L21/7688 ,  H01L27/101

摘要： A method of making a semiconductor device includes forming a pillar shaped semiconductor device surrounded by an insulating layer such that a contact hole in the insulating layer exposes an upper surface of the semiconductor device. The method also includes forming a shadow mask layer over the insulating layer such that a portion of the shadow mask layer overhangs a portion of the contact hole, forming a conductive layer such that a first portion of the conductive layer is located on the upper surface of the semiconductor device exposed in the contact hole and a second portion of the conductive layer is located over the shadow mask layer, and removing the shadow mask layer and the second portion of the conductive layer.

摘要翻译： 制造半导体器件的方法包括形成由绝缘层包围的柱状半导体器件，使得绝缘层中的接触孔露出半导体器件的上表面。 该方法还包括在绝缘层上形成荫罩层，使得阴影掩模层的一部分悬垂在接触孔的一部分上，形成导电层，使得导电层的第一部分位于 暴露在接触孔中的半导体器件和导电层的第二部分位于荫罩层之上，并且去除荫罩层和导电层的第二部分。

公开(公告)号：US20070232031A1

公开(公告)日：2007-10-04

申请号：US11805428

申请日：2007-05-22

申请人： Kaushal Singh ,  David Carlson ,  Manish Hemkar ,  Satheesh Kuppurao ,  Randhir Thakur

发明人： Kaushal Singh ,  David Carlson ,  Manish Hemkar ,  Satheesh Kuppurao ,  Randhir Thakur

IPC分类号： H01L21/20

CPC分类号： H01L21/0262 ,  C23C16/482 ,  C30B25/105 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02661

摘要： A method of preparing a clean substrate surface for blanket or selective epitaxial deposition of silicon-containing and/or germanium-containing films. In addition, a method of growing the silicon-containing and/or germanium-containing films, where both the substrate cleaning method and the film growth method are carried out at a temperature below 750° C., and typically at a temperature from about 700° C. to about 500° C. The cleaning method and the film growth method employ the use of radiation having a wavelength ranging from about 310 nm to about 120 nm in the processing volume in which the silicon-containing film is grown. Use of this radiation in combination with particular partial pressure ranges for the reactive cleaning or film-forming component species enable the substrate cleaning and epitaxial film growth at temperatures below those previously known in the industry.

摘要翻译： 一种制备用于覆盖或选择性外延沉积含硅和/或含锗膜的清洁衬底表面的方法。 此外，生长含硅和/或含锗膜的方法，其中基板清洗方法和膜生长方法都在低于750℃的温度下进行，通常在约700℃的温度下进行 ℃至约500℃。清洁方法和膜生长方法在其中生长含硅膜的处理体积中使用波长为约310nm至约120nm的辐射。 将该辐射与用于反应性清洁或成膜组分物质的特定分压范围的组合的使用使得能够在低于工业以前已知的温度下进行基材清洗和外延膜生长。

公开(公告)号：US20070087506A1

公开(公告)日：2007-04-19

申请号：US11538765

申请日：2006-10-04

申请人： Randhir Thakur

发明人： Randhir Thakur

IPC分类号： H01L21/336

CPC分类号： H01L21/28211 ,  H01L21/02046 ,  H01L21/02049 ,  H01L21/02052 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31662 ,  H01L21/31675 ,  H01L21/76221 ,  H01L29/40114 ,  H01L29/518

摘要： In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation between the clustered process chambers takes place in a controlled environment such as nitrogen or a vacuum. In some embodiments, the method provides an oxide layer to be used as part of the device, such as a tunnel oxide for a flash-EEPROM, or as a general gate oxide. Alternatively, the steps can be used to sculpt through oxidation various levels of a substrate, thereby allowing for embedded memory architecture. Cleaning between oxidation steps offers the advantage of providing a more defect-free oxide layer or providing access to a more defect-free level of substrate.

公开(公告)号：US06955996B2

公开(公告)日：2005-10-18

申请号：US10624817

申请日：2003-07-22

申请人： Daniel F Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam N. Al-Shareef ,  Randhir Thakur

发明人： Daniel F Gealy ,  Dave Chapek ,  Scott DeBoer ,  Husam N. Al-Shareef ,  Randhir Thakur

IPC分类号： C30B33/00 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28202 ,  C30B33/005 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/31662 ,  H01L29/518 ,  Y10S438/903

摘要： A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.