公开(公告)号：US5567634A

公开(公告)日：1996-10-22

申请号：US431765

申请日：1995-05-01

申请人： Francois Hebert ,  Sze-Hon Kwan ,  Izak Bencuya

发明人： Francois Hebert ,  Sze-Hon Kwan ,  Izak Bencuya

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L29/456

摘要： A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.

摘要翻译： 制造沟槽DMOS晶体管结构的方法导致与晶体管的源极和主体与沟槽自对准的接触。 通过自对准接触，可以将从源极和主体接触的边缘到沟槽的边缘的距离最小化。 因此，可以减小沟槽边缘之间的距离。 结果，晶体管的封装密度急剧增加。 这在低导通电阻和更高的电流驱动能力方面产生了大大改进的性能。 在形成用于自接触接触的氧化物间隔物之前，工艺流程使沟槽多晶硅栅极的高度最大化，从而确保间隔物的足够的台阶高度。

公开(公告)号：US5879994A

公开(公告)日：1999-03-09

申请号：US842661

申请日：1997-04-15

申请人： Sze-Hon Kwan ,  Izak Bencuya ,  Steven P. Sapp

发明人： Sze-Hon Kwan ,  Izak Bencuya ,  Steven P. Sapp

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L21/28114 ,  H01L29/42368 ,  H01L29/7802 ,  Y10S148/126 ,  Y10S438/975

摘要： An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed. Gate-drain capacitance caused by polysilicon gate overlap of the substrate is minimized as the overlap is minimized. Because input capacitance is reduced, switching speed is increased. This self-aligned feature also results in a smaller cell pitch dimension and higher packing density. Therefore, the specific ON resistance is reduced and current driving capacity is also greatly elevated.

摘要翻译： 使用有源掩模来蚀刻到n-外延衬底的有源区域中的场氧化物。 栅极氧化物生长后，沉积多晶硅层并进行平面化。 有源掩模定义了用于露台门DMOS结构的多晶硅栅极临界尺寸。 多晶硅栅极的边缘与厚平台栅极氧化物的边缘自对准。 由于不需要层间对准来描绘多晶硅栅极，所以设计不需要提供对准公差。 沉积与阳极氧化物重叠的非关键掩模。 执行在暴露区域中回到场氧化物的蚀刻。 进行氧化物选择性蚀刻以减少源极区域中的氧化物厚度。 进行自对准体植入，体接触掩蔽和植入，以及源掩蔽和植入。 沉积电介质。 沉积源极接触掩膜并进行接触蚀刻。 源金属被沉积，形成钝化层。 当重叠被最小化时，由衬底的多晶硅栅极重叠引起的栅 - 漏电容最小化。 由于输入电容降低，开关速度提高。 这种自对准特征还导致更小的电池间距尺寸和更高的包装密度。 因此，特定的导通电阻降低，电流驱动能力也大大提高。

公开(公告)号：US5665619A

公开(公告)日：1997-09-09

申请号：US645446

申请日：1996-05-13

申请人： Sze-Hon Kwan ,  Izak Bencuya

发明人： Sze-Hon Kwan ,  Izak Bencuya

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L29/456

摘要： A trench DMOS transistor structure includes a contact to the transistor's source and body that is self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low m-resistance and higher current drive capability. Alternate process modules are provided for fabricating the self-aligned contact structure.

摘要翻译： 沟槽DMOS晶体管结构包括与沟槽自对准的晶体管源极和主体的接触。 通过自对准接触，可以将从源极和主体接触的边缘到沟槽的边缘的距离最小化。 因此，可以减小沟槽边缘之间的距离。 结果，晶体管的封装密度急剧增加。 这在低m电阻和更高的电流驱动能力方面产生了大大改进的性能。 提供了用于制造自对准接触结构的交替工艺模块。

公开(公告)号：US5910669A

公开(公告)日：1999-06-08

申请号：US918954

申请日：1992-07-24

申请人： Mike F. Chang ,  Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  King Owyang

发明人： Mike F. Chang ,  Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  King Owyang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/4236

摘要： A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower epitaxial layer. The lightly doped upper epitaxial layer reduces the electric field at the bottom of the trench, thus protecting the gate oxide from breakdown during high voltage operation. Advantageously the upper portion of the lightly doped upper epitaxial layer has little adverse effect on the transistor's on resistance.

摘要翻译： 其栅电极位于沟槽中的DMOS场效应晶体管包括覆盖在通常外延层上的轻掺杂外延层。 沟槽仅穿过上层外延层的一部分，该外延层比下层的下层外延层更轻掺杂。 轻掺杂的上部外延层减小沟槽底部的电场，从而在高电压操作期间保护栅极氧化物不被击穿。 有利地，轻掺杂的上部外延层的上部对晶体管的导通电阻几乎没有不利影响。

公开(公告)号：US5316959A

公开(公告)日：1994-05-31

申请号：US928909

申请日：1992-08-12

申请人： Sze-Hon Kwan ,  Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

发明人： Sze-Hon Kwan ,  Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L21/76 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0619 ,  H01L29/7813

摘要： A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.

摘要翻译： 使用六个掩模步骤制造沟槽DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +区域和晶体管的有源部分。 LOCOS工艺还通过降低氧化物台阶高度来消除现有技术结构中存在的多边形问题。 晶体管端接结构包括几个场环，每组相邻的场环由绝缘沟槽隔开，从而允许场环非常靠近在一起。 场环和沟槽以与有源晶体管的对应部分相同的步骤制造。

公开(公告)号：US5532179A

公开(公告)日：1996-07-02

申请号：US447484

申请日：1995-05-23

申请人： Mike F. Chang ,  Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  King Owyang

发明人： Mike F. Chang ,  Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  King Owyang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335 ,  H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/4236

摘要： A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower epitaxial layer. The lightly doped upper epitaxial layer reduces the electric field at the bottom of the trench, thus protecting the gate oxide from breakdown during high voltage operation. Advantageously the upper portion of the lightly doped upper epitaxial layer has little adverse effect on the transistor's on resistance.

摘要翻译： 其栅电极位于沟槽中的DMOS场效应晶体管包括覆盖在通常外延层上的轻掺杂外延层。 沟槽仅穿过上层外延层的一部分，该外延层比下层的下层外延层更轻掺杂。 轻掺杂的上部外延层减小沟槽底部的电场，从而在高电压操作期间保护栅极氧化物不被击穿。 有利地，轻掺杂的上部外延层的上部对晶体管的导通电阻几乎没有不利影响。

公开(公告)号：US5468982A

公开(公告)日：1995-11-21

申请号：US253527

申请日：1994-06-03

申请人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

发明人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68 ,  H01L21/265

CPC分类号： H01L29/407 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/1095 ,  H01L29/4236

摘要： A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the source region implant step in order to prevent (block) a channel from forming in these corner areas. Punch-through is thereby eliminated and reliability improved, while source/drain on-resistance is only slightly increased. The blocking of the trench corners creates a cutout structure at each trench corner, whereby the source region does not extend to the trench corner, but instead the underlying oppositely-doped body region extends to the trench corner.

摘要翻译： 沟槽的DMOS晶体管具有改进的器件性能和生产产量。 在制造期间，在源区域注入步骤期间，单元沟槽角部，即两个沟槽相交的区域被覆盖在集成电路基板的主表面上，并具有阻挡光致抗蚀剂层，以便防止（阻挡）在这些区域中形成沟道 角落地区。 因此消除了穿通，并提高了可靠性，同时源极/漏极导通电阻仅略微增加。 沟槽拐角的阻塞在每个沟槽角处产生切口结构，由此源极区域不延伸到沟槽角部，而是相反地，下面相对掺杂的体区域延伸到沟槽角部。