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    Load reduced memory module
    3.
    发明申请
    Load reduced memory module 审中-公开
    减少内存模块

    公开(公告)号：US20100312956A1

    公开(公告)日：2010-12-09

    申请号：US12801325

    申请日：2010-06-03

    申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa ,  Shunichi Saito

    发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa ,  Shunichi Saito

    IPC分类号： G06F12/00 ,  G06F3/00

    CPC分类号： G11C5/04 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.

    摘要翻译： 存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。 至少两个存储器芯片被分配给每个数据寄存器缓冲器。 每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于 大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。 根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

    Semiconductor package
    6.
    发明申请
    Semiconductor package 审中-公开
    半导体封装

    公开(公告)号：US20090001548A1

    公开(公告)日：2009-01-01

    申请号：US12213559

    申请日：2008-06-20

    申请人： Fumiyuki Osanai ,  Toshio Sugano ,  Atsushi Hiraishi

    发明人： Fumiyuki Osanai ,  Toshio Sugano ,  Atsushi Hiraishi

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/3011

    摘要： A semiconductor package which includes: a semiconductor chip which includes a signal terminal for inputting and outputting electrical signals and a ground terminal; and a package substrate which includes a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a terminal electrode forming surface on which a signal terminal electrode electrically connected to the signal terminal and a ground terminal electrode electrically connected to the ground terminal are arranged in an array pattern, wherein: on the semiconductor chip mounting surface, there is provided a first signal wiring connected to the signal terminal, a ground wiring connected to the ground terminal, and a ground conductive layer connected to the ground wiring and is provided in a planar pattern in an area excluding the forming area of the first signal wiring; on the terminal electrode forming surface, there is provided a second signal wiring connected to the signal terminal electrode, and a ground fine wiring connected to the ground terminal electrode; and the first signal wiring and the second signal wiring are connected via a conductor filled in a signal through hole penetrating the package substrate, and the ground conductive layer and the ground fine wiring are connected via a conductor filled in a ground through hole penetrating the package substrate.

    摘要翻译： 一种半导体封装件，包括：半导体芯片，其包括用于输入和输出电信号的信号端子和接地端子; 以及包括其上安装有半导体芯片的半导体芯片安装面的封装基板以及与该信号端子电连接的信号端子电极和与接地端子电连接的接地端子电极的端子电极形成面 在阵列图案中，其中：在半导体芯片安装表面上，提供连接到信号端子的第一信号布线，连接到接地端子的接地布线和连接到接地布线的接地导电层，并且设置在 在除了第一信号布线的形成区域之外的区域中的平面图案; 在端子电极形成表面上设置连接到信号端子电极的第二信号布线和连接到接地端子电极的接地精细布线; 并且第一信号布线和第二信号布线经由填充在穿过封装基板的信号通孔中的导体连接，并且接地导体层和接地精细布线经由填充在地面中的导体穿过穿过封装的孔而连接 基质。