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    PARASITIC IMPEDANCE ESTIMATION IN CIRCUIT LAYOUT
    9.
    发明申请
    PARASITIC IMPEDANCE ESTIMATION IN CIRCUIT LAYOUT 审中-公开
    电路布局中的PARASITIC阻抗估计

    公开(公告)号：US20080016478A1

    公开(公告)日：2008-01-17

    申请号：US11777094

    申请日：2007-07-12

    申请人： Robert Lutz ,  Joel Ficke

    发明人： Robert Lutz ,  Joel Ficke

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： The present invention in one embodiment performs estimation of parasitic impedances in a circuit. Leaf cells of circuit components are evaluated such that their parasitic impedances are estimated, and the leaf cells are placed in a physical layout. Parasitic impedances of interconnect wiring is evaluated, and the interconnect wire routing is placed. Parasitic impedance within the circuit is then estimated using a parasitic reduction process.

    摘要翻译： 本发明在一个实施例中执行电路中寄生阻抗的估计。 对电路元件的叶细胞进行评估，以便估计其寄生阻抗，并将叶细胞置于物理布局中。 评估互连布线的寄生阻抗，布置布线。 然后使用寄生减少过程来估计电路内的寄生阻抗。

    Lateral Programmable Polysilicon Structure Incorporating Polysilicon Blocking Diode
    10.
    发明申请
    Lateral Programmable Polysilicon Structure Incorporating Polysilicon Blocking Diode 有权
    结合多晶硅阻挡二极管的横向可编程多晶硅结构

    公开(公告)号：US20060208287A1

    公开(公告)日：2006-09-21

    申请号：US11419558

    申请日：2006-05-22

    申请人： Robert Lutz ,  Thomas Wong

    发明人： Robert Lutz ,  Thomas Wong

    IPC分类号： H01L29/76

    CPC分类号： H01L21/84 ,  G11C17/16 ,  H01L27/11801 ,  H01L27/1203 ,  H01L29/868 ,  Y10S257/91

    摘要： A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

    摘要翻译： 可编程元件包括形成在通过电介质层与半导体衬底隔离的多晶硅层中的二极管和可编程结构。 二极管包括第一区域和相反导电类型的第二区域。 可编程结构包括具有相反导电类型的第三区域和第四区域。 二极管的第一区域和可编程结构的第三区域电连接。 在操作中，当施加超过可编程结构的第一击穿电压的电压以将可编程结构反向偏置时，可编程结构被编程为低阻抗状态。 可编程元件可用于形成具有非常低的寄生电容的可编程阵列，使得能够实现大型和超快速可编程逻辑阵列。