公开(公告)号：US10354871B2

公开(公告)日：2019-07-16

申请号：US15701192

申请日：2017-09-11

Applicant: General Electric Company

Inventor： Stacey Joy Kennerly ,  Victor Torres ,  David Lilienfeld ,  Robert Dwayne Gossman ,  Gregory Keith Dudoff

IPC: H01L21/02 ,  H01L21/04 ,  H01L21/768 ,  H01L23/532 ,  C23C14/16 ,  H01L21/285

Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

公开(公告)号：US20190080906A1

公开(公告)日：2019-03-14

申请号：US15701192

申请日：2017-09-11

Applicant: General Electric Company

Inventor： Stacey Joy Kennerly ,  Victor Torres ,  David Lilienfeld ,  Robert Dwayne Gossman ,  Gregory Keith Dudoff

IPC: H01L21/02 ,  C23C14/16 ,  H01L21/04 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/02697 ,  C23C14/165 ,  H01L21/049 ,  H01L21/28568 ,  H01L21/76877 ,  H01L23/53223

Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

公开(公告)号：US20130146898A1

公开(公告)日：2013-06-13

申请号：US13740734

申请日：2013-01-14

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

IPC: H01L29/49

CPC classification number: H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

Abstract: The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

Abstract translation: 本申请提供了制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极触点与源极之间的距离小于0.6μm。 还提供了一个垂直的SiC MOSFET。

公开(公告)号：US10903330B2

公开(公告)日：2021-01-26

申请号：US14091622

申请日：2013-11-27

Applicant: General Electric Company

Inventor： Richard Joseph Saia ,  Stephen Daley Arthur ,  Zachary Matthew Stum ,  Roger Raymond Kovalec ,  Gregory Keith Dudoff

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L21/3213 ,  H01L21/027

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

公开(公告)号：US20150144960A1

公开(公告)日：2015-05-28

申请号：US14091622

申请日：2013-11-27

Applicant: General Electric Company

Inventor： Richard Joseph Saia ,  Stephen Daley Arthur ,  Zachary Matthew Stum ,  Roger Raymond Kovalec ,  Gregory Keith Dudoff

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/4933 ,  H01L21/0273 ,  H01L21/049 ,  H01L21/32139 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7802

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Abstract translation: 本文公开的主题涉及诸如碳化硅（SiC）功率器件（例如，MOSFET，IGBT等）的金属氧化物半导体（MOS）器件。在一个实施例中，半导体器件包括设置在 半导体层顶部。 半导体器件还包括具有锥形侧壁的栅电极。 此外，栅极包括设置在栅极氧化物层的顶部上的多晶硅层和设置在多晶硅层顶部的金属硅化物层。