-
公开(公告)号:US20150115284A1
公开(公告)日:2015-04-30
申请号:US14396852
申请日:2013-05-15
发明人: Stephen Daley Arthur , Alexander Viktorovich Bolotnikov , Peter Almern Losee , Kevin Sean Matocha , Richard Joseph Saia , Zachary Matthew Stum , Ljubisa Dragoljub Stevanovic , Kuna Venkat Satya Rama Kishore , James William Kretchmer
CPC分类号: H01L29/0638 , H01L21/0465 , H01L29/0619 , H01L29/0646 , H01L29/1608 , H01L29/36 , H01L29/6606 , H01L29/7395 , H01L29/7811 , H01L29/8611 , H01L29/8613
摘要: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.
摘要翻译: 半导体器件包括:包含碳化硅的衬底; 设置在所述衬底上的漂移层,包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域,其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部,所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数,半导体器件的电荷容差大于1.0×1013 / cm2。
-
公开(公告)号:US20150144960A1
公开(公告)日:2015-05-28
申请号:US14091622
申请日:2013-11-27
发明人: Richard Joseph Saia , Stephen Daley Arthur , Zachary Matthew Stum , Roger Raymond Kovalec , Gregory Keith Dudoff
CPC分类号: H01L29/4933 , H01L21/0273 , H01L21/049 , H01L21/32139 , H01L29/1608 , H01L29/42376 , H01L29/66068 , H01L29/7802
摘要: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.
摘要翻译: 本文公开的主题涉及诸如碳化硅(SiC)功率器件(例如,MOSFET,IGBT等)的金属氧化物半导体(MOS)器件。在一个实施例中,半导体器件包括设置在 半导体层顶部。 半导体器件还包括具有锥形侧壁的栅电极。 此外,栅极包括设置在栅极氧化物层的顶部上的多晶硅层和设置在多晶硅层顶部的金属硅化物层。
-
公开(公告)号:US10903330B2
公开(公告)日:2021-01-26
申请号:US14091622
申请日:2013-11-27
发明人: Richard Joseph Saia , Stephen Daley Arthur , Zachary Matthew Stum , Roger Raymond Kovalec , Gregory Keith Dudoff
IPC分类号: H01L29/49 , H01L29/66 , H01L29/423 , H01L29/78 , H01L29/16 , H01L21/04 , H01L21/3213 , H01L21/027
摘要: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.
-
公开(公告)号:US20160307997A1
公开(公告)日:2016-10-20
申请号:US15194774
申请日:2016-06-28
发明人: Stephen Daley Arthur , Alexander Viktorovich Bolotnikov , Peter Almern Losee , Kevin Sean Motocha , Richard Joseph Saia , Zachary Matthew Stum , Ljuibisa Dragolijub Stevanovic , Kuna Venkat Satya Rama Kishore , James William Kretchmer
IPC分类号: H01L29/06 , H01L29/16 , H01L29/861 , H01L29/66 , H01L29/739 , H01L29/78 , H01L29/36 , H01L21/04
CPC分类号: H01L29/0638 , H01L21/0465 , H01L29/0619 , H01L29/0646 , H01L29/1608 , H01L29/36 , H01L29/6606 , H01L29/7395 , H01L29/7811 , H01L29/8611 , H01L29/8613
摘要: A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.
摘要翻译: 半导体器件可以包括包含碳化硅的衬底; 设置在掺杂有第一掺杂剂类型的衬底上的漂移层; 邻近所述漂移层设置的阳极区域,其中所述阳极区域掺杂有第二掺杂剂类型; 以及连接终端延伸部,其邻近所述阳极区域设置并且围绕所述阳极区域延伸,其中所述连接终端延伸部具有宽度并且包括在第一方向和第二方向上分离的多个离散区域,并且以 第二掺杂剂类型,以便具有通常沿着远离主阻塞结的边缘的方向减小的功能形式的第二导电类型的有效掺杂分布。
-
公开(公告)号:US09406762B2
公开(公告)日:2016-08-02
申请号:US14396852
申请日:2013-05-15
发明人: Stephen Daley Arthur , Alexander Viktorovich Bolotnikov , Peter Almern Losee , Kevin Sean Matocha , Richard Joseph Saia , Zachary Matthew Stum , Ljubisa Dragoljub Stevanovic , Kuna Venkat Satya Rama Kishore , James William Kretchmer
IPC分类号: H01L29/36 , H01L29/16 , H01L29/06 , H01L29/739 , H01L29/861 , H01L21/04 , H01L29/66 , H01L29/78
CPC分类号: H01L29/0638 , H01L21/0465 , H01L29/0619 , H01L29/0646 , H01L29/1608 , H01L29/36 , H01L29/6606 , H01L29/7395 , H01L29/7811 , H01L29/8611 , H01L29/8613
摘要: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.
摘要翻译: 半导体器件包括:包含碳化硅的衬底; 设置在所述衬底上的漂移层,包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域,其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部,所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数,半导体器件的电荷容差大于1.0×1013 / cm2。
-
-
-
-