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    Efficient optical proximity correction repair flow method and apparatus
    2.
    发明授权
    Efficient optical proximity correction repair flow method and apparatus 有权
    高效的光学邻近校正修复流程方法和装置

    公开(公告)号：US09250538B2

    公开(公告)日：2016-02-02

    申请号：US14146771

    申请日：2014-01-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guoxiang Ning ,  Christopher Spence ,  Paul Ackmann ,  Chin Teong Lim

    IPC: G06F17/50 ,  G03F7/20 ,  G03F1/70

    CPC classification number: G03F7/70441 ,  G03F1/70 ,  Y02T10/82

    Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

    Abstract translation: 公开了一种用于高效光学邻近校正（OPC）修复流程的方法和装置。 实施例可以包括接收集成电路（IC）设计布局的输入数据流，对输入数据流执行OPC步骤的一个或多个迭代和布局抛光步骤，以及如果最后一个输出的输出执行智能增强步骤 OPC步骤的迭代不能满足一个或多个布局标准，并且如果一个或多个迭代的数量满足阈值。 附加实施例可以包括执行与OPC步骤交联的模式插入过程，模式插入过程是基本光学规则检查（ORC）过程。

    Multiple threshold convergent OPC model
    4.
    发明授权
    Multiple threshold convergent OPC model 有权

    公开(公告)号：US09645486B2

    公开(公告)日：2017-05-09

    申请号：US14560388

    申请日：2014-12-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chin Teong Lim ,  Guoxiang Ning ,  Paul Ackmann

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G03F1/36

    Abstract: Methods of calibrating an OPC model using converged results of CD measurements from at least two locations along a substrate profile of a 1D, 2D, or critical area structure are provided. Embodiments include calibrating an OPC model for a structure to be formed in a substrate; simulating a CD of the structure at at least two locations along a substrate profile of the structure using the OPC model; comparing the simulated CD of the structure at each location against a corresponding measured CD; recalibrating the OPC model based on the comparing of each simulated CD against the corresponding measured CD; repeating the steps of simulating, comparing, and recalibrating until comparing at a first of the at least two locations converges to a first criteria and comparing at each other of the at least two locations converges to a corresponding criteria; and forming the structure using the recalibrated OPC model.

    Achieving a critical dimension target based on resist characteristics
    5.
    发明授权
    Achieving a critical dimension target based on resist characteristics 有权
    实现基于抗蚀剂特性的关键尺寸目标

    公开(公告)号：US09329471B1

    公开(公告)日：2016-05-03

    申请号：US14533497

    申请日：2014-11-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guoxiang Ning ,  Xintuo Dai ,  Huang Liu ,  Chin Teong Lim

    IPC: G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/20 ,  G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/54 ,  G03F1/70 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/34

    Abstract: Achieving a critical dimension target for a feature based on characteristics of a resist is facilitated. Mask data is established for fabricating a lithographic mask to expose different regions of a resist to high, low, and intermediate exposure levels. The resist is configured to exhibit high solubility when exposed to the high or low exposure level, and low solubility when exposed to the intermediate exposure level. A critical dimension for a region of the resist to be exposed to the intermediate exposure level is determined, and the mask data is established to indicate opaque regions for forming on the lithographic mask. The opaque regions are arrayed to facilitate exposing the region of the resist to the intermediate exposure level, to achieve the determined critical dimension. Further, a method is provided for forming in-situ a patterned mask from a mask layer above a substrate material.

    Abstract translation: 实现基于抗蚀剂特性的特征的关键尺寸目标。 建立掩模数据用于制造光刻掩模以将抗蚀剂的不同区域暴露于高，低和中等曝光水平。 抗蚀剂被配置为当暴露于高或低曝光水平时表现出高溶解度，并且当暴露于中等曝光水平时具有低溶解度。 确定抗蚀剂暴露于中间曝光水平的区域的关键尺寸，并且建立掩模数据以指示用于在光刻掩模上形成的不透明区域。 排列不透明区域以便于将抗蚀剂的区域暴露于中间曝光水平，以获得确定的临界尺寸。 此外，提供了一种用于从衬底材料上方的掩模层原位形成图案化掩模的方法。

    Hard mask etch and dielectric etch aware overlap for via and metal layers
    7.
    发明授权
    Hard mask etch and dielectric etch aware overlap for via and metal layers 有权

    公开(公告)号：US09817927B2

    公开(公告)日：2017-11-14

    申请号：US14841037

    申请日：2015-08-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guo Xiang Ning ,  Yuping Ren ,  David Power ,  Lalit Shokeen ,  Chin Teong Lim ,  Paul W. Ackmann ,  Xiang Hu

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5009 ,  G03F1/36 ,  G06F17/5081

    Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

    METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOUT OF AN INTEGRATED CIRCUIT
    8.
    发明申请
    METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOUT OF AN INTEGRATED CIRCUIT 有权
    测试细胞和细胞的方法包括在集成电路中的布局

    公开(公告)号：US20160328510A1

    公开(公告)日：2016-11-10

    申请号：US14703179

    申请日：2015-05-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guido Ueberreiter ,  Paul Ackmann ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Chin Teong Lim

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/14 ,  Y02P90/265

    Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

    Abstract translation: 一种方法包括接收包括多个层的集成电路的布局，选择一个层并提供一个或多个瓦片数值。 基于瓦片数值将集成电路的管芯区域划分为多个瓦片。 确定在布局的基础上，如果瓦片中所选择的一个层的一部分具有用于包含测试单元或虚拟单元的可用空间，并且将指示结果的标签分配给 瓦。 根据所分配的标签确定是否满足一个或多个空间可用性标准，并且如果满足，则将标签用于在布局中放置一个或多个测试单元和一个或多个虚拟单元中的至少一个 。

    Alternating space decomposition in circuit structure fabrication
    9.
    发明授权
    Alternating space decomposition in circuit structure fabrication 有权

    公开(公告)号：US09606432B2

    公开(公告)日：2017-03-28

    申请号：US14533464

    申请日：2014-11-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Guoxiang Ning ,  Xintuo Dai ,  Huang Liu ,  Chin Teong Lim

    IPC: G03F7/00 ,  G03F7/09 ,  G03F7/20

    CPC classification number: G03F7/0035 ,  G03F7/094 ,  G03F7/2024 ,  G03F7/203

    Abstract: Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.

    Reticle, system comprising a plurality of reticles and method for the formation thereof
    10.
    发明授权
    Reticle, system comprising a plurality of reticles and method for the formation thereof 有权
    掩模版，系统包括多个掩模版及其形成方法

    公开(公告)号：US09535319B2

    公开(公告)日：2017-01-03

    申请号：US14674157

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

    IPC: G03F1/36 ,  G03F7/30 ,  H01L21/768

    CPC classification number: G03F1/36

    Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

    Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

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