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公开(公告)号:US10056453B2
公开(公告)日:2018-08-21
申请号:US15217643
申请日:2016-07-22
Applicant: GLOBALFOUNDRIES INC.
IPC: H01L29/06 , H01L23/00 , H01L29/20 , H01L29/16 , H01L29/267 , H01L21/02 , H01L21/308 , H01L21/3065
CPC classification number: H01L29/0657 , H01L21/02381 , H01L21/0243 , H01L21/02458 , H01L21/02488 , H01L21/02507 , H01L21/0254 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L23/562 , H01L29/16 , H01L29/2003 , H01L29/267
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.
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公开(公告)号:US10355043B2
公开(公告)日:2019-07-16
申请号:US15635608
申请日:2017-06-28
Applicant: GLOBALFOUNDRIES INC.
Inventor: Ajey P. Jacob , Deepak K. Nayak , Srinivasa R. Banna
IPC: H01L29/78 , H01L29/08 , H01L29/16 , H01L33/32 , H01L29/417 , H01L33/36 , H01L29/778 , H01L33/00 , H01L27/15 , H01L29/66 , H01L29/20 , H01L29/10 , H01L29/872
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.
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公开(公告)号:US20180026096A1
公开(公告)日:2018-01-25
申请号:US15217643
申请日:2016-07-22
Applicant: GLOBALFOUNDRIES INC.
IPC: H01L29/06 , H01L29/20 , H01L21/3065 , H01L29/267 , H01L21/02 , H01L21/308 , H01L23/00 , H01L29/16
CPC classification number: H01L29/0657 , H01L21/02381 , H01L21/0254 , H01L21/3065 , H01L21/3083 , H01L23/562 , H01L29/16 , H01L29/2003 , H01L29/267
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.
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公开(公告)号:US10217900B2
公开(公告)日:2019-02-26
申请号:US15643061
申请日:2017-07-06
Applicant: GLOBALFOUNDRIES INC.
Inventor: Deepak K. Nayak , Srinivasa R. Banna , Ajey P. Jacob
Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.
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公开(公告)号:US20190013337A1
公开(公告)日:2019-01-10
申请号:US15642017
申请日:2017-07-05
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Deepak K. Nayak , Srinivasa Banna
Abstract: An integrated circuit (IC) microdisplay structure is disclosed. The structure can include: a first oxide layer positioned on a substrate; a first voltage source (VSS) pad within the first oxide layer; a metal pillar disposed within the first oxide layer and on the first VSS pad; a first gallium nitride layer disposed on the metal pillar and extending over the first oxide layer; and at least one subpixel formed from the first gallium nitride layer. Alternatively, the structure can include a first oxide layer positioned on a substrate; a first metal layer positioned on the first oxide layer; a first gallium nitride layer on the first metal layer; and at least one subpixel formed from the first gallium nitride layer. The structure may further include a subpixel driver electrically connected to the at least one subpixels where a portion of the subpixel driver is vertically aligned with a subpixel.
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公开(公告)号:US10177178B1
公开(公告)日:2019-01-08
申请号:US15642017
申请日:2017-07-05
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Deepak K. Nayak , Srinivasa Banna
Abstract: An integrated circuit (IC) microdisplay structure is disclosed. The structure can include: a first oxide layer positioned on a substrate; a first voltage source (VSS) pad within the first oxide layer; a metal pillar disposed within the first oxide layer and on the first VSS pad; a first gallium nitride layer disposed on the metal pillar and extending over the first oxide layer; and at least one subpixel formed from the first gallium nitride layer. Alternatively, the structure can include a first oxide layer positioned on a substrate; a first metal layer positioned on the first oxide layer; a first gallium nitride layer on the first metal layer; and at least one subpixel formed from the first gallium nitride layer. The structure may further include a subpixel driver electrically connected to the at least one subpixels where a portion of the subpixel driver is vertically aligned with a subpixel.
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