公开(公告)号：US10580897B2

公开(公告)日：2020-03-03

申请号：US16046368

申请日：2018-07-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej J. Pawlak

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/165

Abstract: Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.

公开(公告)号：US20180026096A1

公开(公告)日：2018-01-25

申请号：US15217643

申请日：2016-07-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Srinivasa R. Banna ,  Deepak K. Nayak ,  Bartlomiej J. Pawlak

IPC: H01L29/06 ,  H01L29/20 ,  H01L21/3065 ,  H01L29/267 ,  H01L21/02 ,  H01L21/308 ,  H01L23/00 ,  H01L29/16

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/562 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.

公开(公告)号：US10453750B2

公开(公告)日：2019-10-22

申请号：US15629884

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej J. Pawlak ,  Guillaume Bouche ,  Ajey P. Jacob

IPC: H01L25/07 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775

Abstract: Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

公开(公告)号：US10056453B2

公开(公告)日：2018-08-21

申请号：US15217643

申请日：2016-07-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Srinivasa R. Banna ,  Deepak K. Nayak ,  Bartlomiej J. Pawlak

IPC: H01L29/06 ,  H01L23/00 ,  H01L29/20 ,  H01L29/16 ,  H01L29/267 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/562 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.

公开(公告)号：US09978836B1

公开(公告)日：2018-05-22

申请号：US15344862

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej J. Pawlak

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66568 ,  H01L29/78

Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed. The source/drain region is comprised of a first layer of a first semiconductor material having a first electronic band gap and a second layer of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material.

公开(公告)号：US09824933B1

公开(公告)日：2017-11-21

申请号：US15232174

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej J. Pawlak

IPC: H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/768 ,  H01L29/80 ,  H01L21/8234 ,  H01L29/786 ,  H01L23/522 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823487 ,  H01L21/8221 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/78642

Abstract: Structures and fabrication methods for a vertical-transport field-effect transistor. A plurality of pillars comprised of a semiconductor material are formed. First and second gate structures are located along a length of the pillars. The second gate structure is vertically spaced along the length of the pillars relative to the first gate structure. The first and second gate structures are each associated with a channel defined in the pillars.

公开(公告)号：US20180374946A1

公开(公告)日：2018-12-27

申请号：US16046368

申请日：2018-07-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej J. Pawlak

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696

Abstract: Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.

公开(公告)号：US10134901B1

公开(公告)日：2018-11-20

申请号：US15632922

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej J. Pawlak

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/423

Abstract: Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.

公开(公告)号：US20180130878A1

公开(公告)日：2018-05-10

申请号：US15344862

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej J. Pawlak

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66568 ,  H01L29/78

Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. A nanostructure, a gate structure coupled with the nanostructure, and a source/drain region coupled with an end of the nanostructure are formed. The source/drain region is comprised of a first layer of a first semiconductor material having a first electronic band gap and a second layer of a second semiconductor material having a second electronic band gap that is wider than the first electronic band gap of the first semiconductor material.