公开(公告)号：US08889500B1

公开(公告)日：2014-11-18

申请号：US13960244

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/338 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.

Abstract translation: 本文公开的一种说明性方法包括形成限定翅片的多个翅片形成沟槽，在沟槽内和翅片上方形成第一应力层，并在第一应力层上执行至少一个蚀刻工艺，以便 以限定至少部分地位于鳍片的相对侧上的沟槽内的第一应力层的间隔开的部分。 该方法还包括在第一层的间隔开的部分上方形成第二应力层的间隔开的部分，在第二层间隔开的部分之间形成翅片之上的第三应力层，在形成第三层之后 在第二层和第三层上形成导电层。

公开(公告)号：US20150041906A1

公开(公告)日：2015-02-12

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, JR.

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

公开(公告)号：US20140361379A1

公开(公告)日：2014-12-11

申请号：US14466103

申请日：2014-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Derya Deniz

IPC: H01L27/092 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: Approaches are provided for forming a semiconductor device (e.g., a FET) having a multi-function layer (e.g., niobium carbide (NbC)) that serves as a work function layer and a gate metal layer in gate stacks of solid state applications. By introducing a single layer with multiple functions, total number of layers that needs processing (e.g., recessing) may be decreased. As such, the complexity of device integration and resulting complications may be reduced.

Abstract translation: 提供了用于形成具有作为功函数层的多功能层（例如，碳化铌（NbC））的半导体器件（例如，FET）和用于固态应用的栅堆叠中的栅极金属层的方法。 通过引入具有多个功能的单层，可以减少需要处理（例如，凹陷）的层的总数。 因此，可能会降低器件集成的复杂性和导致的并发症。

公开(公告)号：US09076787B2

公开(公告)日：2015-07-07

申请号：US14536737

申请日：2014-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Derya Deniz

IPC: H01L29/51 ,  H01L21/283 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/45 ,  H01L29/456 ,  H01L29/78

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract translation: 提供具有n型晶体管和具有有源区的p型晶体管的半导体器件。 有源区还包括两个相邻的门结构。 选择性地去除两个相邻栅极结构之间的介电层的一部分，以形成具有底部和活性区上侧壁的接触开口。 双层衬垫选择性地设置在n型晶体管的接触开口内，单层衬垫设置在p型晶体管的接触开口内。 n型晶体管和p型晶体管中的接触开口填充有接触材料。 处理单层衬垫以在p型晶体管中形成缺乏镍的硅化物。

公开(公告)号：US08975142B2

公开(公告)日：2015-03-10

申请号：US13870854

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Abhijeet Paul ,  Abner Bello ,  Vimal K. Kamineni ,  Derya Deniz

IPC: H01L29/786 ,  H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract translation: 通过在通道上施加物理应力的结构来增强FinFET的性能。 应力通过用于源极和漏极的钨触点，外延生长的升高源和升高的漏极的组合以及钨接触沉积的方面的操作来实现，从而导致钨的固有应力的增强。 通过外延重新生长升高的源极和漏极的部分，通过蚀刻用于触点的沟槽和/或蚀刻在鳍的表面下方的较深的沟槽（和相应的更长的触点）来进一步增强应力。

公开(公告)号：US08912057B1

公开(公告)日：2014-12-16

申请号：US13910370

申请日：2013-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Derya Deniz

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/80 ,  H01L21/70 ,  H01L21/283 ,  H01L29/45

CPC classification number: H01L29/517 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/45 ,  H01L29/456 ,  H01L29/78

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract translation: 提供具有n型晶体管和具有有源区的p型晶体管的半导体器件。 有源区还包括两个相邻的门结构。 选择性地去除两个相邻栅极结构之间的介电层的一部分，以形成具有底部和活性区上侧壁的接触开口。 双层衬垫选择性地设置在n型晶体管的接触开口内，单层衬垫设置在p型晶体管的接触开口内。 n型晶体管和p型晶体管中的接触开口填充有接触材料。 处理单层衬垫以在p型晶体管中形成缺乏镍的硅化物。

公开(公告)号：US09583397B1

公开(公告)日：2017-02-28

申请号：US15151720

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Derya Deniz ,  Benjamin G. Moser ,  Sunit S. Mahajan ,  Domingo A. Ferrer Luppi

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/45 ,  H01L21/3205 ,  H01L21/3215 ,  H01L21/768 ,  H01L21/321 ,  H01L21/285 ,  H01L21/266

CPC classification number: H01L21/823814 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32053 ,  H01L21/3212 ,  H01L21/3215 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76859 ,  H01L21/76889 ,  H01L21/823871 ,  H01L29/45 ,  H01L29/785

Abstract: One aspect of the disclosure relates to a contact within a dielectric layer to a source/drain terminal of a field-effect-transistor (FET). The contact may include: a titanium-tantalum-silicide at a surface of the source/drain terminal; a barrier layer over the titanium-tantalum-silicide; and a metal over the barrier layer and extending to a top surface of the dielectric layer.

Abstract translation: 本公开的一个方面涉及电介质层中与场效应晶体管（FET）的源极/漏极端子的接触。 接触可以包括：在源极/漏极端子的表面处的钛 - 钽 - 硅化物; 在钛 - 钽 - 硅化物上的阻挡层; 以及阻挡层上的金属并延伸到电介质层的顶表面。

公开(公告)号：US09117930B2

公开(公告)日：2015-08-25

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。