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    METHODS OF FORMING AIR GAPS IN METALLIZATION LAYERS ON INTEGRATED CIRCUIT PRODUCTS
    2.
    发明申请
    METHODS OF FORMING AIR GAPS IN METALLIZATION LAYERS ON INTEGRATED CIRCUIT PRODUCTS 有权
    在集成电路产品中形成金属层中的空气GAPS的方法

    公开(公告)号：US20170047242A1

    公开(公告)日：2017-02-16

    申请号：US14822258

    申请日：2015-08-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhiguo Sun ,  Qiang Fang ,  Christian Witt

    IPC: H01L21/764 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

    CPC classification number: H01L21/764 ,  H01L21/02068 ,  H01L21/02356 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/53295

    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least one damage-causing process operation to selectively damage portions of the insulating material adjacent the trenches, forming a conductive line in each of the trenches, after forming the conductive lines, performing a selective etching process to selectively remove at least portions of the damaged portions of the insulating material and thereby define an air gap positioned laterally adjacent each of the conductive lines, and forming a capping layer of material above the conductive lines, the air gap and the undamaged portion of the layer of insulating material.

    Abstract translation: 本文公开的一种说明性方法除其他外包括在绝缘材料层中形成多个沟槽，执行至少一个损坏造成处理操作以选择性地损坏邻近沟槽的绝缘材料的部分，在每个沟槽中形成导电线 在形成导电线之后，执行选择性蚀刻工艺以选择性地去除绝缘材料的损坏部分的至少一部分，从而限定横向邻近每条导电线的气隙，并且形成覆盖层 导电线上方的材料，空气间隙和绝缘材料层的未损坏部分。

    Liner and cap layer for placeholder source/drain contact structure planarization and replacement
    3.
    发明授权
    Liner and cap layer for placeholder source/drain contact structure planarization and replacement 有权
    衬垫和盖层用于占位符源/漏接触结构的平面化和替换

    公开(公告)号：US09466723B1

    公开(公告)日：2016-10-11

    申请号：US14751718

    申请日：2015-06-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Haigou Huang ,  Qiang Fang ,  Jin Ping Liu ,  Huang Liu

    IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/283 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/535

    CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method includes forming a placeholder source/drain contact structure above a semiconductor material. A conformal deposition process is performed to form a liner layer above the placeholder contact structure. A dielectric layer is formed above the liner layer. A first planarization process is performed to remove material of the dielectric layer and expose a first top surface of the liner layer above the placeholder contact structure. A first cap layer is formed above the dielectric layer. A second planarization process is performed to remove material of the first cap layer and the liner layer to expose a second top surface of the placeholder contact structure. The placeholder contact structure is removed to define a source/drain contact recess in the dielectric layer. The sidewalls of the dielectric layer in the source/drain contact recess are covered by the liner layer. A conductive material is formed in the contact recess.

    Abstract translation: 一种方法包括在半导体材料之上形成占位符源极/漏极接触结构。 执行保形沉积工艺以在占位符接触结构之上形成衬垫层。 在衬层上方形成介电层。 执行第一平面化处理以去除电介质层的材料并将衬垫层的第一顶表面暴露在占位符接触结构之上。 在电介质层上方形成第一盖层。 执行第二平面化处理以去除第一盖层和衬垫层的材料以暴露占位符接触结构的第二顶表面。 去除占位符接触结构以在电介质层中限定源极/漏极接触凹部。 源极/漏极接触凹部中的电介质层的侧壁被衬里层覆盖。 导电材料形成在接触凹部中。

    Method to prevent cobalt recess
    5.
    发明授权
    Method to prevent cobalt recess 有权

    公开(公告)号：US10109521B1

    公开(公告)日：2018-10-23

    申请号：US15606895

    申请日：2017-05-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Qiang Fang ,  Shafaat Ahmed ,  Changhong Wu ,  Zhiguo Sun ,  Jiehui Shu

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

    Abstract: A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.

    SELF-ALIGNED MULTIPLE PATTERNING PROCESSES WITH LAYERED MANDRELS
    7.
    发明申请
    SELF-ALIGNED MULTIPLE PATTERNING PROCESSES WITH LAYERED MANDRELS 审中-公开

    公开(公告)号：US20190318931A1

    公开(公告)日：2019-10-17

    申请号：US15950364

    申请日：2018-04-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jiehui Shu ,  Xiaohan Wang ,  Qiang Fang ,  Zhiguo Sun ,  Jinping Liu ,  Hui Zang

    IPC: H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

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