公开(公告)号：US09685334B1

公开(公告)日：2017-06-20

申请号：US15134917

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yue Ke ,  Mohammad Hasanuzzaman ,  Benjamin G. Moser ,  Shahrukh A. Khan ,  Sean M. Polvino

IPC: H01L21/225 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/2254 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/2257 ,  H01L29/66795

Abstract: Methods of forming a semiconductor fin and methods for controlling dopant diffusion to a semiconductor fin are disclosed herein. The methods provide alternative ways to incorporate a carbon dopant into the fin to later control out-diffusion of dopants from a dopant-including epitaxial layer. One method includes depositing a carbon-containing layer over a portion of the fin adjacent to the gate and annealing to diffuse carbon from the carbon-containing layer into at least the portion of the semiconductor fin. This method can be applied to SOI or bulk semiconductor substrates. Another method includes epitaxially growing a carbon dopant containing semiconductor layer for later use in forming the fin.

公开(公告)号：US09892979B2

公开(公告)日：2018-02-13

申请号：US14744198

申请日：2015-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kriteshwar K. Kohli ,  Sean M. Polvino

IPC: H01J35/00 ,  H01L21/66 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L22/12 ,  H01L21/845 ,  H01L22/30 ,  H01L29/66795

Abstract: A semiconductor device or article includes a substrate including a feature and divided into a feature region in which the feature is formed and a pad region in which the substrate is substantially unmodified, and a layer of interest applied over the substrate and feature. The pad and feature regions are irradiated and resulting photoelectron intensities are recorded and used to determine a thickness of the layer of interest over the feature. In addition, if the layer of interest includes an atomic species distinct from any in the substrate, an actual dose of the atomic species can be determined.

公开(公告)号：US20160372385A1

公开(公告)日：2016-12-22

申请号：US14744198

申请日：2015-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kriteshwar K. Kohli ,  Sean M. Polvino

IPC: H01L21/66 ,  H01J49/00 ,  H01L29/66 ,  H01J49/44

CPC classification number: H01L22/12 ,  H01L21/845 ,  H01L22/30 ,  H01L29/66795

Abstract: A semiconductor device or article includes a substrate including a feature and divided into a feature region in which the feature is formed and a pad region in which the substrate is substantially unmodified, and a layer of interest applied over the substrate and feature. The pad and feature regions are irradiated and resulting photoelectron intensities are recorded and used to determine a thickness of the layer of interest over the feature. In addition, if the layer of interest includes an atomic species distinct from any in the substrate, an actual dose of the atomic species can be determined.

Abstract translation: 一种半导体器件或制品包括包括特征并分成其中形成特征的特征区域的衬底和其中衬底基本上未改性的焊盘区域，以及施加在衬底和特征上的感兴趣层。 照射垫和特征区域并记录所得到的光电子强度并用于确定该特征上的感兴趣层的厚度。 此外，如果感兴趣的层包括与底物中的任何一个不同的原子种类，则可以确定原子种类的实际剂量。

公开(公告)号：US09806161B1

公开(公告)日：2017-10-31

申请号：US15092910

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahrukh A. Khan ,  Unoh Kwon ,  Shahab Siddiqui ,  Sean M. Polvino ,  Joseph F. Shepard, Jr.

IPC: H01L29/423 ,  H01L21/311 ,  H01L29/51 ,  H01L21/033 ,  H01L21/84 ,  H01L21/027 ,  H01L21/8234 ,  H01L27/12

CPC classification number: H01L29/42364 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/28202 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1207 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

公开(公告)号：US20170294519A1

公开(公告)日：2017-10-12

申请号：US15092910

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahrukh A. Khan ,  Unoh Kwon ,  Shahab Siddiqui ,  Sean M. Polvino ,  Joseph F. Shepard, JR.

IPC: H01L29/423 ,  H01L21/027 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/12 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L29/42364 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/28202 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1207 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

Abstract: One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.