公开(公告)号：US20170077234A1

公开(公告)日：2017-03-16

申请号：US14853303

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Neeraj TRIPATHI ,  Srinivasa R. BANNA

IPC: H01L29/161 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/02532 ,  H01L21/0245 ,  H01L21/02664 ,  H01L21/76208

Abstract: Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films for semiconductor devices are provided. One method includes, for instance: obtaining a wafer including a substrate; epitaxially growing at least one first silicon germanium (SiGe) layer over the wafer; and epitaxially growing at least one second SiGe layer over the at least one first SiGe layer. One device includes, for instance: a wafer including a substrate; at least one first layer of semiconductor material disposed over the wafer; at least one second layer of semiconductor material disposed over the at least one first layer of semiconductor material; and at least one first and second openings, each opening extending through the at least one second layer of semiconductor material, the at least one first layer of semiconductor material, and a portion of the substrate.

Abstract translation: 提供了用于半导体器件的外延生长的晶格失配膜的弹性松弛的装置和方法。 一种方法包括例如：获得包括衬底的晶片; 在晶片上外延生长至少一个第一硅锗（SiGe）层; 以及在所述至少一个第一SiGe层上外延生长至少一个第二SiGe层。 一个装置包括例如：包括衬底的晶片; 设置在所述晶片上方的至少一个第一半导体材料层; 设置在所述至少一个第一半导体材料层上的至少一个第二半导体材料层; 以及至少一个第一和第二开口，每个开口延伸穿过所述至少一个第二半导体材料层，所述至少一个第一半导体材料层和所述衬底的一部分。

公开(公告)号：US20190058082A1

公开(公告)日：2019-02-21

申请号：US15678385

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak K. NAYAK ,  Srinivasa R. BANNA ,  Ajey P. JACOB

IPC: H01L33/00 ,  H01L33/06 ,  H01L33/08 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniform semiconductor nanowire and nanosheet light emitting diodes and methods of manufacture. The structure includes a buffer layer; at least one dielectric layer on the buffer layer, the at least one dielectric layer having a plurality of openings exposing the buffer layer; and a plurality of uniformly sized and shaped nanowires or nanosheets formed in the openings and extending above the at least one dielectric layer.

公开(公告)号：US20190013436A1

公开(公告)日：2019-01-10

申请号：US15643061

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak K. NAYAK ,  Srinivasa R. BANNA ,  Ajey P. JACOB

IPC: H01L33/12 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/22

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.

公开(公告)号：US20190006413A1

公开(公告)日：2019-01-03

申请号：US15635608

申请日：2017-06-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. JACOB ,  Deepak K. NAYAK ,  Srinivasa R. BANNA

IPC: H01L27/15 ,  H01L29/08 ,  H01L29/78 ,  H01L33/32 ,  H01L29/16 ,  H01L29/417 ,  H01L33/36 ,  H01L29/778 ,  H01L33/00 ,  H01L29/66 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L27/15 ,  H01L25/167 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7827 ,  H01L29/872 ,  H01L33/007 ,  H01L33/32 ,  H01L33/36 ,  H01L33/38 ,  H01L2933/0016

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.