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公开(公告)号:US20180277427A1
公开(公告)日:2018-09-27
申请号:US15988145
申请日:2018-05-24
Applicant: GLOBALFOUNDRIES INC.
Inventor: Viraj SARDESAI , Suraj K. PATIL , Scott BEASOR , Vimal Kumar KAMINENI
IPC: H01L21/768 , H01L23/532 , H01L23/522
CPC classification number: H01L21/76849 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76843 , H01L21/76877 , H01L21/76886 , H01L21/76889 , H01L23/5226 , H01L23/53209
Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
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公开(公告)号:US20200152749A1
公开(公告)日:2020-05-14
申请号:US16742981
申请日:2020-01-15
Applicant: GLOBALFOUNDRIES INC.
Inventor: Hui ZANG , Guowei XU , Keith TABAKMAN , Viraj SARDESAI
IPC: H01L29/417 , H01L27/088 , H01L21/768 , H01L21/311 , H01L21/28 , H01L29/66
Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
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公开(公告)号:US20180166402A1
公开(公告)日:2018-06-14
申请号:US15373898
申请日:2016-12-09
Applicant: GLOBALFOUNDRIES INC.
Inventor: Viraj SARDESAI , William HENSON , Domingo FERRER LUPPI , Scott ALLEN , Emre ALPTEKIN
IPC: H01L23/62 , H01L21/768 , H01L23/528 , H01L23/522 , H01L23/532
CPC classification number: H01L23/53252 , H01L21/76816 , H01L21/76834 , H01L23/5228 , H01L23/5256 , H01L23/5283
Abstract: A semiconductor device includes a metal thin film such as an eFUSE or a precision resistor above and laterally displaced from an interconnect structure. A first dielectric layer is disposed over the interconnect structure and optionally under the metal thin film, and is adapted to prevent etching of the interconnect structure during patterning of the metal thin film. Contacts to the metal thin film and the interconnect are made through a second dielectric layer that is disposed over the metal thin film and over the interconnect.
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公开(公告)号:US20190221650A1
公开(公告)日:2019-07-18
申请号:US15873565
申请日:2018-01-17
Applicant: GLOBALFOUNDRIES INC.
Inventor: Hui ZANG , Guowei XU , Keith TABAKMAN , Viraj SARDESAI
IPC: H01L29/417 , H01L21/768 , H01L21/311 , H01L27/088 , H01L21/28
Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.
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公开(公告)号:US20180130703A1
公开(公告)日:2018-05-10
申请号:US15347119
申请日:2016-11-09
Applicant: GLOBALFOUNDRIES INC.
Inventor: Viraj SARDESAI , Suraj K. PATIL , Scott BEASOR , Vimal Kumar KAMINENI
IPC: H01L21/768 , H01L23/522 , H01L23/532
CPC classification number: H01L21/76849 , H01L21/76802 , H01L21/76843 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53209
Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
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