公开(公告)号：US20170186669A1

公开(公告)日：2017-06-29

申请号：US15461538

申请日：2017-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian KLEWER

IPC: H01L23/48 ,  H01L29/78 ,  H01L23/528 ,  H01L21/768 ,  H01L29/06 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/53238 ,  H01L29/0649 ,  H01L29/772 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

公开(公告)号：US20170040274A1

公开(公告)日：2017-02-09

申请号：US15296770

申请日：2016-10-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Luke ENGLAND ,  Christian KLEWER

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03011 ,  H01L2224/03616 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2225/06527 ,  H01L2224/80001 ,  H01L2924/00014

Abstract: Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

Abstract translation: 公开了用于制备3D集成半导体器件和所得到的器件的方法。 实施例包括分别在第一和第二半导体器件上形成第一和第二接合焊盘，第一和第二接合焊盘分别具有多个金属段，第一接合焊盘的金属段具有不同于 第二接合焊盘的金属段或者具有与第二接合焊盘的金属段的构造相同的配置，但是相对于第二接合焊盘旋转; 以及通过所述第一和第二接合焊盘将所述第一和第二半导体器件接合在一起。

公开(公告)号：US20160111386A1

公开(公告)日：2016-04-21

申请号：US14515969

申请日：2014-10-16

Applicant: Globalfoundries Inc.

Inventor： Luke ENGLAND ,  Christian KLEWER

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03011 ,  H01L2224/03616 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2225/06527 ,  H01L2224/80001 ,  H01L2924/00014

Abstract: Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

Abstract translation: 公开了用于制备3D集成半导体器件和所得到的器件的方法。 实施例包括分别在第一和第二半导体器件上形成第一和第二接合焊盘，第一和第二接合焊盘分别具有多个金属段，第一接合焊盘的金属段具有不同于 第二接合焊盘的金属段或者具有与第二接合焊盘的金属段的构造相同的配置，但是相对于第二接合焊盘旋转; 以及通过所述第一和第二接合焊盘将所述第一和第二半导体器件接合在一起。

公开(公告)号：US20150243582A1

公开(公告)日：2015-08-27

申请号：US14186360

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian KLEWER

IPC: H01L23/48 ,  H01L21/285 ,  H01L21/02 ,  H01L29/417 ,  H01L21/321 ,  H01L29/16 ,  H01L29/06 ,  H01L21/768 ,  H01L21/3065

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/53238 ,  H01L29/0649 ,  H01L29/772 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.

Abstract translation: 公开了在单个沉积工艺期间形成TSV隔离层和晶体管至BEOL隔离层的方法以及所得到的器件。 实施例包括提供栅堆叠，其相对侧的源/漏区和硅衬底上的STI层; 通过STI层和硅衬底形成横向与栅堆叠分离的TSV沟槽; 在所述TSV沟槽的侧壁和底表面上以及所述栅叠层，所述STI层和所述硅衬底之上形成隔离层; 在TSV沟槽中形成TSV; 在隔离层和TSV上形成电介质盖; 以及通过介电盖和隔离层形成源极/漏极接触点，直到源极/漏极接合区域。