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    METHOD AND STRUCTURE FOR LOW-K FACE-TO-FACE BONDED WAFER DICING
    2.
    发明申请
    METHOD AND STRUCTURE FOR LOW-K FACE-TO-FACE BONDED WAFER DICING 审中-公开
    用于低K面对面粘结波浪方法和方法的方法和结构

    公开(公告)号：US20170062399A1

    公开(公告)日：2017-03-02

    申请号：US14833209

    申请日：2015-08-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke ENGLAND ,  Ramakanth ALAPATI

    IPC: H01L25/00 ,  H01L23/00 ,  H01L21/3105 ,  H01L23/48 ,  H01L21/311 ,  H01L21/268 ,  H01L25/065 ,  H01L21/82 ,  H01L21/768

    CPC classification number: H01L25/50 ,  H01L21/268 ,  H01L21/78 ,  H01L24/11 ,  H01L24/17 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/83896 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16251

    Abstract: Methods for removing low-k dielectric material from dicing lanes in a bonded pair of IC wafers and the resulting device are disclosed. Embodiments include providing low-k dielectric and standard dielectric layers on upper surfaces of top and bottom IC substrates, each including an array of adjacent IC die areas separated by dicing lanes; removing from the dicing lanes the standard and low-k dielectric layers to form cavities exposing sections of the upper surfaces of IC substrates; depositing a standard dielectric material in the cavities and on upper surfaces of the standard dielectric layer of the top and bottom IC substrates; planarizing upper surfaces of the standard dielectric material of the IC substrates; forming a face-to-face bonding of the IC substrates, wherein the dicing lanes in the IC substrates are vertically aligned; and dicing adjacent bonded IC die areas through vertically aligned dicing lanes in the IC substrates.

    Abstract translation: 公开了一种用于从结合的IC晶片对中的切割通道中除去低k介电材料的方法以及所得到的器件。 实施例包括在顶部和底部IC基板的上表面上提供低k电介质和标准电介质层，每个包括由切割通道分隔开的相邻IC管芯区域的阵列; 从切割线移除标准和低k电介质层以形成暴露IC基板的上表面的部分的空腔; 在空腔中和顶部和底部IC基板的标准电介质层的上表面上沉积标准电介质材料; 平面化IC基板的标准介电材料的上表面; 形成IC基板的面对面接合，其中IC基板中的切割通道垂直对齐; 并通过IC基板中的垂直排列的切割通道切割相邻的接合IC芯片区域。

    METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR
    3.
    发明申请
    METHOD AND DEVICE FOR AN INTEGRATED TRENCH CAPACITOR 有权
    集成式电容器的方法和装置

    公开(公告)号：US20150200242A1

    公开(公告)日：2015-07-16

    申请号：US14155886

    申请日：2014-01-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke ENGLAND

    IPC: H01L49/02 ,  H01L21/48 ,  H01L23/498

    CPC classification number: H01L28/60 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L28/90 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.

    Abstract translation: 公开了一种通过提供高电容，超低剖面电容器结构和所得到的器件的集成工艺在插入晶片上形成沟槽电容器的方法。 实施例包括在插入物晶片的正面上形成聚合物嵌段，图案化和蚀刻聚合物嵌段以形成一个或多个沟槽，以及在聚合物嵌段的上表面和一个或多个沟槽中形成电容器。

    FABRICATION OF MULTILAYER CIRCUIT ELEMENTS
    9.
    发明申请
    FABRICATION OF MULTILAYER CIRCUIT ELEMENTS 有权
    多层电路元件的制造

    公开(公告)号：US20160013262A1

    公开(公告)日：2016-01-14

    申请号：US14326659

    申请日：2014-07-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Luke ENGLAND ,  Mahesh Anant BHATKAR ,  Wanbing YI ,  Juan Boon TAN

    IPC: H01L49/02 ,  H01L21/311 ,  H01L21/78 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/324 ,  H01L21/033 ,  H01L21/288

    CPC classification number: H01L28/10 ,  H01L21/0335 ,  H01L21/2885 ,  H01L21/31058 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed. In one embodiment, the conductive portion(s) and the other conductive portion(s) define, at least in part, a conductive coil(s) of the element.

    Abstract translation: 提供了形成诸如多层电感器或变压器的电路元件的晶片级方法。 所述方法包括例如：在衬底上的至少一层中形成电路元件的至少一个导电部分; 提供至少部分地覆盖所述元件的导电部分并且覆盖所述元件的导电部分的未固化的聚合物 - 电介质材料; 部分固化聚合物 - 电介质材料以获得部分硬化的聚合物电介质材料; 并将部分硬化的聚合物电介质材料抛光至导电部分。 抛光使部分硬化的聚合物 - 电介质材料平坦化并且暴露导电部分的上表面，以便于在导电部分上方形成与元件电连接的元件的至少一个其它导电部分。 抛光后，完成聚合物 - 电介质材料的固化。 在一个实施例中，导电部分和另一个导电部分至少部分地限定该元件的导电线圈。

    INTERCONNECT STRUCTURE
    10.
    发明申请
    INTERCONNECT STRUCTURE 审中-公开

    公开(公告)号：US20190035731A1

    公开(公告)日：2019-01-31

    申请号：US15664484

    申请日：2017-07-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Luke ENGLAND ,  Mark W. KUEMERLE

    IPC: H01L23/525 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L23/5256 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5384

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an interconnect structure to connect between different package configurations and methods of manufacture. The structure includes an interconnect comprising a plurality of conductive levels and columns configured into a grid pattern within an insulator material, the plurality of conductive levels and columns aligned to connect to different package configurations; and a control circuit that provides a signal to the interconnect to connect to a combination of the different package configurations.

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