公开(公告)号：US20200135545A1

公开(公告)日：2020-04-30

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. SRIVASTAVA ,  Sipeng GU ,  Sunil K. SINGH ,  Xinyuan DOU ,  Akshey SEHGAL ,  Zhiguo SUN

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US20150255353A1

公开(公告)日：2015-09-10

申请号：US14197267

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Andy WEI ,  Jinping LIU ,  Xiang HU ,  Dae-han CHOI ,  Dae Geun YANG ,  Churamani GAIRE ,  Akshey SEHGAL

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L27/0924

Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.

Abstract translation: 公开了用单个掩模版形成FinFET源极/漏极区域的方法以及所得到的器件。 实施例可以包括在衬底上形成第一鳍片和第二鳍片，形成跨越第一鳍片和第二鳍片的栅极，在栅极的两侧去除第一鳍片和第二鳍片的部分，在第二鳍片上形成硅磷顶部 第一鳍片和第二鳍片代替部分，去除第一鳍片上的磷磷顶部，并且在第一鳍片上形成硅锗顶部代替硅磷顶部。

公开(公告)号：US20150287595A1

公开(公告)日：2015-10-08

申请号：US14725430

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy WEI ,  Mariappan HARIHARAPUTHIRAN ,  Dae Geun YANG ,  Dae-Han CHOI ,  Xiang HU ,  Richard J. CARTER ,  Akshey SEHGAL

IPC: H01L21/033 ,  H01L29/78 ,  H01L21/027

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US20150115418A1

公开(公告)日：2015-04-30

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy WEI ,  Mariappan HARIHARAPUTHIRAN ,  Dae Geun YANG ,  Dae-Han CHOI ,  Xiang HU ,  Richard J. CARTER ,  Akshey SEHGAL

IPC: H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

公开(公告)号：US20180286982A1

公开(公告)日：2018-10-04

申请号：US15475873

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bharat V. KRISHNAN ,  Timothy J. MCARDLE ,  Rinus Tek Po LEE ,  Shishir K. Ray ,  Akshey SEHGAL

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7848 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.

公开(公告)号：US20180226294A1

公开(公告)日：2018-08-09

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David Michael PERMANA ,  Guillaume BOUCHE ,  Andy WEI ,  Mark ZALESKI ,  Anbu Selvam KM MAHALINGAM ,  Craig Michael CHILD, JR. ,  Roderick Alan AUGUR ,  Shyam PAL ,  Linus JANG ,  Xiang HU ,  Akshey SEHGAL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20150198435A1

公开(公告)日：2015-07-16

申请号：US14155504

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alok VAID ,  Abner BELLO ,  Sipeng GU ,  Lokesh SUBRAMANY ,  Xiang HU ,  Akshey SEHGAL

IPC: G01B11/06 ,  H01L21/66

CPC classification number: H01L22/12 ,  G01B11/02 ,  G01B11/0633 ,  G01B11/065 ,  G01B2210/56 ,  G01N21/211 ,  G03F7/70616 ,  G03F7/70625

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract translation: 获得电路结构层的厚度的测量，其中使用光学临界尺寸（OCD）测量技术测量层的厚度，并且层包括高k层和界面层。 分别获得高k层的厚度的测量，其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比，单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性，如界面层的厚度，部分使用单独获得的高k层的厚度测量来确定。