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    CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
    4.
    发明申请
    CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME 有权
    与半导体基板的接触及其形成方法

    公开(公告)号：US20160358860A1

    公开(公告)日：2016-12-08

    申请号：US14729298

    申请日：2015-06-03

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

    IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L23/53266 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238

    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

    Abstract translation: 本发明的一个方面包括在半导体衬底上的电介质层中形成接触的方法。 该方法可以包括：在半导体衬底上的电介质层中形成接触开口以暴露半导体衬底的上部; 沉积第一衬里层以共形地涂覆所述接触开口; 导致第一衬里层的一部分扩散到半导体衬底的上部，以在半导体衬底的上部形成第一混合区; 在第一混合区域上沉积难熔金属层; 以及在接触开口中沉积金属从而形成接触。

    Method for growing strain-inducing materials in CMOS circuits in a gate first flow
    7.
    发明授权
    Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
    在栅极第一流中在CMOS电路中增长应变诱导材料的方法

    公开(公告)号：US08779525B2

    公开(公告)日：2014-07-15

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
    8.
    发明申请
    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
    在门电路第一流程中生长应变诱导材料的方法

    公开(公告)号：US20130161759A1

    公开(公告)日：2013-06-27

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L27/092

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

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