公开(公告)号：US20170104100A1

公开(公告)日：2017-04-13

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V.V.S. Surisetty ,  Mickey H. Yu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

公开(公告)号：US20160358860A1

公开(公告)日：2016-12-08

申请号：US14729298

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238

Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

Abstract translation: 本发明的一个方面包括在半导体衬底上的电介质层中形成接触的方法。 该方法可以包括：在半导体衬底上的电介质层中形成接触开口以暴露半导体衬底的上部; 沉积第一衬里层以共形地涂覆所述接触开口; 导致第一衬里层的一部分扩散到半导体衬底的上部，以在半导体衬底的上部形成第一混合区; 在第一混合区域上沉积难熔金属层; 以及在接触开口中沉积金属从而形成接触。

公开(公告)号：US09390928B2

公开(公告)日：2016-07-12

申请号：US14059842

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Hari V. Mallela ,  Reinaldo Vega

IPC: H01L21/28 ,  H01L29/772 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/28008 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/772

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

Abstract translation: 可以增强栅极电极和源极和漏极区域的下部之间的电容耦合，同时抑制栅极电极和横向间隔开的元件之间的电容耦合，例如用于源极和漏极区域的接触通孔结构。 使用一次性栅极间隔物形成包括栅极和源极和漏极区的晶体管。 去除一次性栅极间隔物以形成间隔腔，其填充有各向异性介电材料以形成各向异性栅极间隔物。 各向异性介电材料与电场对准，使得各向异性介电材料的分子的纵向方向在间隔空腔内垂直排列。 各向异性栅极间隔沿垂直方向提供较高介电常数，沿水平方向提供较低介电常数。

公开(公告)号：US20160118298A1

公开(公告)日：2016-04-28

申请号：US14992669

申请日：2016-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

IPC: H01L21/768 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L21/76886 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

公开(公告)号：US10707167B2

公开(公告)日：2020-07-07

申请号：US15826939

申请日：2017-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/285

Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

公开(公告)号：US09691658B1

公开(公告)日：2017-06-27

申请号：US15159186

申请日：2016-05-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Raghu Mangu ,  Cung D. Tran ,  Domingo A. Ferrer

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/76865 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266

Abstract: A method of forming an electrical contact in an integrated circuit, and an integrated circuit are disclosed. In an embodiment, the integrated circuit comprises a substrate, an insulating layer, and a metal layer. An opening is formed through the insulating layer to expose an active area of the substrate. The metal layer forms a cusp at a top end of the opening, narrowing this end of the opening. In embodiments, the method comprises depositing a conductive layer in the opening to form a liner, applying a filler material inside the opening to protect a portion of the liner, removing the cusp to widen the top of the opening while the filler material protects the portion of the liner covered by this material, removing the filler material from the opening, re-lining the opening, and filling the opening with a conductive material to form a contact through the insulating layer.

公开(公告)号：US09379012B2

公开(公告)日：2016-06-28

申请号：US14992669

申请日：2016-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/423 ,  H01L29/417 ,  H01L21/285 ,  H01L27/092 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76886 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

公开(公告)号：US09818873B2

公开(公告)日：2017-11-14

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V. V. S. Surisetty ,  Mickey H. Yu

IPC: H01L29/40 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

公开(公告)号：US09865546B2

公开(公告)日：2018-01-09

申请号：US14729298

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/53266 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238

Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

公开(公告)号：US09530684B2

公开(公告)日：2016-12-27

申请号：US15172366

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Viraj Yashawant Sardesai ,  Cung Do Tran ,  Reinaldo Ariel Vega

IPC: H01L31/0312 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L23/373

CPC classification number: H01L21/76224 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/02664 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/3738 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/785

Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.

Abstract translation: 本发明的实施例提供了finFET器件中的热抑制的结构和方法。 翅片形成在半导体衬底中。 石墨烯层形成在翅片的侧壁的下部。 浅沟槽隔离区域设置在结构上并且覆盖石墨烯层，而翅片的上部从浅沟槽隔离区域突出。 石墨烯层也可以沉积在基底半导体衬底的顶表面上。 与其它介电材料相比，石墨烯用于将散热物从翅片导出。